Fan-Out Semiconductor Package Pillars With Stepped Opening Lithography
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Solution Overview
Problem
Existing fan-out wafer-level package manufacturing processes face defects in forming openings for connecting pillars due to high aspect ratios, leading to incomplete removal of photoresist material and potential cracks in the connecting structure.
Innovation Solution
Utilizing a phase shift mask to form openings with stepped portions in the photoresist material layer, allowing for the creation of connecting pillars with a large aspect ratio and reduced footprint, and ensuring a larger contact area with the molding layer to prevent crack propagation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional photolithography is used to form openings for connecting pillars, then the manufacturing process is simple, but defects occur due to high aspect ratios leading to incomplete photoresist removal and potential cracks
Solution Approach 1:
The opening formation process is segmented into multiple steps using a multi-layer photomask system. The first photomask forms a preliminary opening pattern, and the second photomask refines it to achieve the final precise geometry. This segmentation allows better control over high aspect ratio openings, preventing incomplete photoresist removal and structural cracks while maintaining manufacturing feasibility.
2Reliability
If connecting pillars are made with larger footprint to ensure structural integrity, then crack propagation is prevented, but the package size increases and miniaturization is compromised
Solution Approach 1:
The connecting pillar structure is given non-uniform local quality through its multi-layer construction. Different material layers are deposited with specific properties optimized for their functions: adhesion promotion at interfaces, mechanical strength in the body, and stress distribution at critical regions. This allows the pillar to maintain high reliability with minimal footprint by concentrating structural enhancements only where needed rather than uniformly increasing the entire pillar dimensions.
3Manufacturing precision
If multiple photomask layers are used to achieve precise opening patterns, then manufacturing precision is improved, but device complexity and process steps increase
Solution Approach 1:
The second photomask layer serves multiple functions simultaneously: it defines the final opening pattern geometry, controls the aspect ratio of openings, provides alignment reference for subsequent processing steps, and enables selective area formation. This multi-functionality reduces the need for additional dedicated process steps, thereby limiting the increase in device complexity despite the added precision capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution prevents defects in the opening formation process and enhances the reliability of the semiconductor package by maintaining structural integrity despite thermal expansion differences, ensuring a smaller footprint and higher aspect ratio for the connecting pillars.
Implementation Method 1
forming an opening having a stepped portion by performing an exposure process on the photoresist material layer using a phase shift mask including a first area, a second area, and a third area, wherein the first area is an area that transmits light of a first wavelength, the second area is an area that does not transmit light of the first wavelength, and the third area is an area that partially transmits the light of the first wavelength
Data Source
AI summary
A semiconductor package is provided. The semiconductor package includes a first redistribution layer, a first semiconductor chip disposed on the first redistribution layer, a molding layer disposed on the first redistribution layer to cover a side surface of the first semiconductor chip, a second redistribution layer disposed on the molding layer, and a connecting pillar disposed to penetrate the molding layer and configured to connect the first redistribution layer to the second redistribution layer, the connecting pillar including a lower area having a first width in a first direction parallel to an upper surface of the first semiconductor chip and an upper area integrally connected to the lower area and having a second width that is less than the first width in the first direction.