Fanout Processor Architecture for Low-Latency Rate-Matched Streaming

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Solution Overview

Problem

Current solutions fail to simultaneously address latency, throughput, and data stream errors in real-time data processing for continuous big data streams with varying transmission and consumption rates across multiple recipients.

Innovation Solution

A processor architecture with TCP client and server circuits, a fanout circuit, and a register that configures transmission rates and message sizes for efficient data interleaving and fanning out to multiple recipients, ensuring reliable, error-checked data transmission.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If data streams are processed and fanned out to multiple recipients, then throughput is improved, but latency increases

Engineering Contradiction:

ImprovethroughputVSAvoidlatency

Core Design Contradiction:

ProductivityVSLoss of time

Solution Approach 1:

The system segments data streams into individual data messages that can be independently processed and routed. The fanout circuit divides the incoming data stream into multiple parallel output streams, allowing simultaneous delivery to multiple recipients without sequential processing delays

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The system performs preliminary configuration of transmission rates and message sizes in registers before data processing begins. This pre-configuration allows the fanout circuit to immediately route data messages at optimized rates without real-time calculation delays, reducing latency while maintaining high throughput

Inventive Principle:

Principle #10Preliminary action

2Productivity

If transmission rates are increased to handle large data volumes, then throughput is improved, but data errors increase

Engineering Contradiction:

ImprovethroughputVSAvoiddata errors

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The system dynamically adjusts transmission rate parameters for each recipient based on their consumption capabilities. The fanout circuit retrieves configured transmission rates from registers and applies them to control the flow of data messages, ensuring high throughput while maintaining data integrity by matching transmission speeds to recipient processing capacities

Inventive Principle:

Principle #35Parameter changes

3Adaptability or versatility

If multiple recipients receive data at different consumption rates, then adaptability is improved, but system complexity increases

Engineering Contradiction:

Improverate matchingVSAvoidsystem complexity

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The fanout circuit performs multiple functions simultaneously: it receives data streams, retrieves transmission rates from registers, controls message sizing, and routes data to multiple recipients at different rates. This multi-functionality in a single circuit reduces overall system complexity while providing high adaptability to different recipient requirements

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The register acts as an intermediary between the fanout circuit and the configuration parameters. It stores pre-configured transmission rates and message sizes, allowing the fanout circuit to efficiently retrieve and apply different rates for multiple recipients without complex real-time negotiation or control logic

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS12363184B2Fanout processor

Publication Date: 2025.07.15 BGC PARTNERS LP

AI summary

Disclosed herein is a processor to process streaming data. The processor includes a TCP client circuit and a TCP server circuit. A fanout circuit is communicatively coupled to the TCP client circuit and the TCP server circuit. The fanout circuit receives data from the TCP client circuit, determines a rate at which to transmit the received market data, and instructs the TCP server circuit to send the received data at the determined rate.