Fan-Out Packaging RDL Plating with a Base Metal Layer
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Solution Overview
Problem
Conventional semiconductor packaging processes face issues with uneven dielectric layers and deteriorated surface topology due to poor quality plating layers in the RDL process, leading to increased contact resistance and impedance, which hinder high-frequency operation.
Innovation Solution
A method involving the formation of a base metal layer on a partial area of a fan-out packaging substrate, followed by the creation of a first dielectric layer with via holes, a redistribution layer, and a second dielectric layer to form a bump structure, enhancing the quality of the plating process and reducing alignment errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the plating speed is increased to improve productivity, then the production efficiency is improved, but the quality of the plating layer deteriorates leading to uneven dielectric layers and increased contact resistance
Solution Approach 1:
A base metal layer is introduced as an intermediary between the substrate and the RDL wiring layer. This base metal layer serves as a foundation that improves the quality of the plating layer, enabling high-quality plating even at higher plating speeds. The base metal layer acts as a mediator that transfers the beneficial effects to the subsequent dielectric and wiring layers.
Solution Approach 2:
The base metal layer is formed in advance before the RDL process begins. This preliminary action prepares the surface with improved topography and electrical properties, ensuring that subsequent plating operations can proceed at higher speeds without compromising quality. The preliminary formation of the base metal layer prevents the deterioration that would otherwise occur during fast plating.
2Manufacturing precision
If the plating process conditions are improved to enhance plating layer quality, then the contact resistance is reduced, but the process time is extended reducing productivity
Solution Approach 1:
The base metal layer is formed preliminarily with optimized conditions to create an ideal surface for subsequent plating. This preliminary preparation allows the RDL plating to be performed more quickly while maintaining high quality, as the base metal layer already provides the necessary surface properties for excellent plating adhesion and uniformity.
Solution Approach 2:
The plating process is segmented into two distinct stages: formation of the base metal layer and formation of the RDL wiring layer. This segmentation allows each stage to be optimized independently - the base metal layer can be formed with conditions optimized for quality, while the RDL layer can be formed with conditions optimized for speed, achieving both high quality and high productivity.
3Device complexity
If multiple dielectric layers are formed between plating processes to create multi-layer RDL wiring, then the wiring complexity is increased, but the surface topology deteriorates due to plating layer quality issues causing unevenness
Solution Approach 1:
The base metal layer serves as a fundamental intermediary that underlies the entire multi-layer RDL structure. It provides a uniformly flat surface that supports multiple dielectric layers and wiring layers without the surface topology deterioration that would otherwise occur. This intermediary layer ensures that even complex multi-layer structures maintain good surface uniformity.
Solution Approach 2:
The base metal layer provides locally improved quality at the interface between the substrate and the RDL structure. By concentrating the quality improvement function in this specific location, the patent enables the rest of the multi-layer structure to be formed with good surface topology, even as complexity increases with additional layers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The base metal layer improves the surface topology of dielectric layers and redistribution layers, reducing contact resistance, enabling stable electrical operation and high-frequency performance while facilitating efficient dicing and reducing manufacturing defects.
Implementation Method 1
forming a wiring layer using copper plating
Data Source
Figure 1A~1D
Figure 2A~2B
Figure 2C~3
AI summary
Disclosed is a method of manufacturing a fan-out packaging device using wafer or panel level packaging including forming a base metal layer on a partial area of a fan-out packaging substrate, forming a first dielectric layer on the base metal layer, patterning the first dielectric layer to form a via hole, forming a redistribution layer (RDL) on the first dielectric layer and the via hole, forming a second dielectric layer on the redistribution layer (RDL), and patterning the second dielectric layer to form a bump structure connected to the redistribution layer.