Fan-Out Package RDL Formation via Substrate Removal
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Solution Overview
Problem
Current semiconductor packaging technologies face challenges in achieving fine pitch redistribution layers (RDL) with ultra-narrow pitches, such as 2 μm or less, which are difficult and costly to manufacture, and require complex processes, while also struggling to meet the smaller form factor requirements of advanced semiconductor devices.
Innovation Solution
A method involving the formation of a semiconductor device with a substrate, a conductive layer, and encapsulants, where a first conductive layer with fine pitch traces is formed over the substrate, followed by disposing a semiconductor die and forming an interconnect structure, allowing for the removal of the substrate and subsequent deposition of a second encapsulant, enabling the creation of both fine pitch and dual-side RDLs with embedded passive devices and vertical interconnect units.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional packaging technologies are used to form fine pitch RDL with ultra-narrow pitches (2 μm or less), then manufacturing precision is improved, but device complexity and manufacturing cost increase significantly
Solution Approach 1:
The substrate is removed before forming the build-up interconnect structure, allowing the RDL to be formed directly on the encapsulated semiconductor die without requiring complex alignment and bonding processes to a temporary carrier. This preliminary removal of the substrate simplifies subsequent manufacturing steps while maintaining ultra-narrow pitch capability.
Solution Approach 2:
The manufacturing process is segmented into distinct phases: first forming the RDL with ultra-narrow pitch on the substrate, then removing the substrate, and finally forming the build-up interconnect structure. This segmentation allows each phase to be optimized independently, achieving high precision RDL formation without the complexity of integrated processes.
2Stability of the object's composition
If temporary carrier bonding is used to prevent warpage during build-up interconnect structure formation, then structural stability is improved, but manufacturing time and cost increase
Solution Approach 1:
The substrate is removed before forming the build-up interconnect structure, eliminating the need for temporary carrier bonding and debonding operations. This preliminary substrate removal prevents warpage issues from arising in the first place, as the RDL is formed directly on the encapsulated die with proper mechanical support, thereby reducing manufacturing time and eliminating additional process steps.
Solution Approach 2:
The substrate is extracted and removed from the structure before the build-up interconnect formation process. This extraction eliminates the need for temporary carriers that would otherwise be required to provide mechanical support and prevent warpage, streamlining the manufacturing process.
3Manufacturing precision
If ultra-fine pitch RDL (2 μm or less) is formed using conventional methods, then manufacturing precision is improved, but manufacturing cost increases
Solution Approach 1:
The substrate is removed before forming the build-up interconnect structure, allowing ultra-fine pitch RDL to be formed using standard photolithography and deposition processes without requiring specialized equipment or complex process control. This preliminary substrate removal enables cost-effective manufacturing of ultra-narrow pitch structures.
Solution Approach 2:
Instead of forming the build-up interconnect structure first and then removing the substrate (which would require complex alignment and bonding), the invention inverts the sequence by removing the substrate first and then forming the RDL and build-up structure. This inversion simplifies the process and reduces manufacturing costs while achieving ultra-fine pitch precision.
4Device complexity
If substrate removal is performed before build-up interconnect structure formation, then device complexity is reduced, but structural stability may be compromised
Solution Approach 1:
The substrate is removed before forming the build-up interconnect structure, and the semiconductor die is first encapsulated in a first encapsulant that provides mechanical support. This preliminary substrate removal is enabled by the encapsulation, which maintains structural stability during and after substrate removal while simplifying subsequent processing steps.
Solution Approach 2:
The first encapsulant acts as an intermediary that provides mechanical support and structural stability after substrate removal. This encapsulant enables the substrate to be removed without compromising the structural integrity of the semiconductor device, allowing simplified processing while maintaining stability.
Data Source
AI summary
A semiconductor device has a first conductive layer including a plurality of conductive traces. The first conductive layer is formed over a substrate. The conductive traces are formed with a narrow pitch. A first semiconductor die and second semiconductor die are disposed over the first conductive layer. A first encapsulant is deposited over the first and second semiconductor die. The substrate is removed. A second encapsulant is deposited over the first encapsulant. A build-up interconnect structure is formed over the first conductive layer and second encapsulant. The build-up interconnect structure includes a second conductive layer. A first passive device is disposed in the first encapsulant. A second passive device is disposed in the second encapsulant. A vertical interconnect unit is disposed in the second encapsulant. A third conductive layer is formed over second encapsulant and electrically connected to the build-up interconnect structure via the vertical interconnect unit.