Fan-Out Semiconductor Package Rear Redistribution Layer
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Solution Overview
Problem
Existing fan-out semiconductor packages require complex and costly processes for implementing redistribution layers, particularly for heat dissipation and pin matching in modules like Wi-Fi, which complicates the manufacturing and integration with main boards.
Innovation Solution
A simplified process for implementing a fan-out semiconductor package with a redistribution layer by laminating it on the surface of an encapsulant, including a supporting member with a cavity and wiring structure, and using connection vias to connect the redistribution layers, allowing for direct mounting on a main board without the need for additional lithography steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a rear redistribution layer is added for heat dissipation and pin matching, then thermal and electrical characteristics are improved, but manufacturing complexity increases due to additional lithography processes
Solution Approach 1:
The patent applies preliminary action by forming the rear redistribution layer pattern on the supporting member before mounting the semiconductor chip. This allows the redistribution layer to be prepared in advance, eliminating the need for additional lithography processes after chip mounting, thus reducing manufacturing complexity while maintaining improved thermal and electrical characteristics
2Adaptability or versatility
If multiple lithography processes are used for redistribution layer formation, then routing flexibility is improved, but manufacturing cost and process time increase
Solution Approach 1:
The patent forms the redistribution layer pattern on the supporting member before chip mounting, allowing routing design to be completed in advance. This preliminary action enables routing flexibility to be achieved without requiring multiple post-mounting lithography processes, thereby improving manufacturing efficiency and productivity
Data Source
AI summary
A method for manufacturing a semiconductor package includes disposing a semiconductor chip having contact pads, and a connection structure around the semiconductor chip on a supporting substrate, with the contact pads facing the supporting substrate, forming an encapsulant encapsulating the semiconductor chip and the connection structure on the supporting substrate, embedding a wiring pattern having a connection portion in the encapsulant, the connection portion having a connection hole, forming a through hole penetrating the encapsulant in the connection hole, the through hole exposing a portion of an upper surface of the connection structure, and forming a conductive via in the through hole, the conductive via connecting the wiring pattern to the connection structure.