Fan-out redistribution layers for semiconductor chip stacking
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Solution Overview
Problem
Current semiconductor device packaging technologies face challenges in efficiently connecting multiple chips without the need for through-silicon vias (TSVs), particularly in reducing parasitic capacitance and handling difficulties during chip stacking and assembly, while maintaining high reliability and cost-effectiveness.
Innovation Solution
The semiconductor device employs a stacked structure with an upper layer chip, first and second resin layers, and interconnect layers made from organic polymer materials, which include polyimide resin and copper, to connect memory and logic chips directly to external circuits via fan-in and fan-out redistribution layers, eliminating the need for TSVs and allowing for reduced substrate thickness and parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through-silicon via (TSV) technology is used to connect stacked chips, then electrical connection between chips is achieved, but parasitic capacitance increases and manufacturing complexity increases
Solution Approach 1:
The patent extracts the connection function from the silicon substrate itself (TSV approach) and relocates it to organic resin layers with embedded conductors. By taking out the via structure from the silicon chip and placing it in the organic substrate, the patent eliminates the need for penetrating the silicon, thereby reducing parasitic capacitance while maintaining electrical connection reliability.
Solution Approach 2:
The patent introduces organic resin layers with embedded conductors as an intermediary between the stacked chips and the external circuit board. This intermediary layer provides the necessary electrical connections without requiring direct penetration through the silicon chips, thus reducing parasitic capacitance while achieving reliable electrical connectivity.
2Adaptability or versatility
If TSV-based chip stacking is used, then three-dimensional integration is achieved, but handling difficulty and manufacturing complexity increase
Solution Approach 1:
The patent segments the connection structure into separate functional layers: chip stacking layer, organic resin interconnect layer, and circuit board layer. This segmentation allows each layer to be optimized independently, with the organic resin layer providing flexible handling and routing capabilities without the constraints of rigid TSV structures, thereby improving manufacturability while maintaining 3D integration.
Solution Approach 2:
The patent changes the material parameter from rigid silicon-based TSVs to flexible organic resin with embedded conductors. This parameter change allows for easier handling, bending, and routing during assembly while maintaining the three-dimensional chip stacking capability, thus improving ease of manufacture without sacrificing adaptability.
3Adaptability or versatility
If fan-out redistribution layers are used to extend connections outside chip, then external circuit connectivity is improved, but device complexity increases
Solution Approach 1:
The patent merges the redistribution layer function with the substrate structure itself. Instead of adding separate complex redistribution layers, the organic resin substrate integrates both structural support and electrical routing functions, providing fan-out connectivity while simplifying the overall device structure and reducing complexity.
Data Source
AI summary
According to one embodiment, the first resin layer is provided on the first face of the upper layer chip. The first interconnect layer is electrically connected to the upper layer chip. The second resin layer extends into a region outside chip. The region is outer side of a side face of the upper layer chip. The second interconnect layer is provided in the second resin layer. The second interconnect layer is connected to the first interconnect layer and extending into the region outside chip. The lower layer chip is mounted on the surface side of the first resin layer, and is connected to the first interconnect layer. The first sealing resin covers the upper layer chip.