Fan-Out Package Redistribution Layers for Large PCB-Matched Packages
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Solution Overview
Problem
The semiconductor industry faces challenges in miniaturization and packaging techniques for stacked semiconductor devices, particularly in achieving high bandwidth and thermal expansion matching with printed circuit boards, while maintaining reliability and simplifying the manufacturing process for large package applications.
Innovation Solution
The integration of an integrated fan out (InFO) process with an Ajinomoto build up film (ABF) or prepreg lamination, along with a composite redistribution layer, allows for the formation of a semiconductor device with multiple chips and redistribution layers, enabling high bandwidth and thermal expansion matching with printed circuit boards, and simplifying the manufacturing process for large package applications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If stacked and bonded semiconductor devices are used to reduce physical size, then integration density improves, but manufacturing complexity increases
Solution Approach 1:
The patent combines the InFO process with ABF or prepreg lamination processes into a unified manufacturing flow. Multiple redistribution layers and die stacking operations are merged into a single integrated process sequence, reducing the number of separate manufacturing steps while achieving high integration density and small form factor
2Reliability
If sophisticated bonding techniques are used for stacked semiconductor devices, then electrical connection reliability improves, but process complexity increases
Solution Approach 1:
The patent utilizes controlled parameters such as temperature, pressure, and material composition during the bonding process. By optimizing these parameters within specific ranges, reliable electrical connections are achieved through standardized processes rather than complex multi-step procedures, maintaining high yield while simplifying manufacturing
3Power
If large package sizes are used for high bandwidth applications, then bandwidth exceeds 1 TbE, but thermal expansion matching with PCB becomes more difficult
Solution Approach 1:
The patent employs composite redistribution layers combining multiple materials with different thermal expansion coefficients. These composite structures are designed to match the thermal expansion properties of both the semiconductor dies and the PCB substrate, enabling large package sizes with bandwidth exceeding 1 TbE while maintaining reliable thermal-mechanical integration
4Power
If multiple redistribution layers are formed for high bandwidth, then electrical performance improves, but manufacturing steps increase
Solution Approach 1:
The patent forms multiple redistribution layers in advance during the initial manufacturing sequence, integrating them into the substrate before die stacking. This preliminary formation of complex interconnect structures eliminates the need for additional post-bonding processing steps, achieving high electrical performance while maintaining manufacturing efficiency
Data Source
AI summary
An integrated fan out package is utilized in which the dielectric materials of different redistribution layers are utilized to integrate the integrated fan out package process flows with other package applications. In some embodiments an Ajinomoto or prepreg material is utilized as the dielectric in at least some of the overlying redistribution layers.