Fan-Out Package Redistribution Layer Width Variation
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Solution Overview
Problem
Fan-out semiconductor packages face challenges in enhancing board level reliability, particularly in temperature cycle and drop tests, due to the complexity of redistribution layers with both fan-in and fan-out regions, which current methods fail to effectively address.
Innovation Solution
The design of redistribution layers with varying line widths, where the second line portion has a greater width than the first, passing through the boundary between fan-in and fan-out regions, and the inclusion of dummy patterns in high-stress corner portions to mitigate stress effects, enhances the board level reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the redistribution layer uses a uniform line width, then the manufacturing process is simple, but the board level reliability is poor due to stress concentration at the fan-in/fan-out boundary
Solution Approach 1:
The redistribution layer employs different line widths in different regions: a first line width in the fan-in region and a second line width (greater than the first) in the fan-out region. This local variation in geometric properties allows the structure to better distribute stress at the boundary between fan-in and fan-out regions, thereby improving board level reliability without requiring complex multi-layer or curved designs.
2Reliability
If the redistribution layer has a complex structure with varying line widths, then the stress distribution is improved, but the manufacturing precision requirements increase
Solution Approach 1:
The redistribution layer is segmented into distinct regions with different line widths. The first line portion has a first line width and the second line portion has a second line width greater than the first. This segmentation allows each region to be optimized for its specific function while maintaining manufacturability through clear, discrete geometric definitions that are easier to control than continuous variations.
3Volume of moving object
If the semiconductor chip size is reduced, then the package size is compact, but the number of pins that can be implemented is limited
Solution Approach 1:
The fan-out package structure redistributes connection terminals outwardly from the semiconductor chip region to the fan-out region. This dimensional expansion allows connection terminals to be positioned outside the chip's projected area, enabling a greater number of pins to be implemented while maintaining a compact package footprint. The redistribution layer extends the electrical connections beyond the chip boundaries, effectively utilizing the substrate area.
Data Source
AI summary
A fan-out semiconductor package includes: a semiconductor chip; an encapsulant encapsulating at least portions of the semiconductor chip; and a first connection member disposed on an active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads of the semiconductor chip. The redistribution layer includes a line pattern having a first line portion having a first line width and a second line portion connected to the first line portion and having a second line width, greater than the first line width, a fan-in region is a projected surface of the semiconductor chip projected in a direction perpendicular to the active surface, a fan-out region is a region surrounding the fan-in region, and the second line portion at least passes through a boundary between the fan-in region and the fan-out region.