Integrated Fan-Out Package Routing Angles for Thermal Stress
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Solution Overview
Problem
As semiconductor dies become smaller, conventional packaging technologies face challenges in increasing the number of I/O pads due to limited pitch and solder ball size, leading to issues like solder bridges and reduced yield.
Innovation Solution
The development of an Integrated Fan-Out (InFO) package structure and method, which involves a carrier substrate with a release layer, through vias for electrical connections, redistribution layers for flexible pin-out contacts, and die-to-die metal connections routed at angles to reduce stress and increase reliability during thermal cycling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If conventional packaging technology is used with smaller dies, then the die size is reduced, but the number of I/O pads is limited due to limited pitch and solder ball size
Solution Approach 1:
The patent transitions from traditional fan-in packaging where I/O pads are confined to the die surface to fan-out packaging where the I/O pad array is redistributed onto a larger package substrate. This dimensional expansion allows the same number of I/O pads to be accommodated on a larger area, effectively increasing the number of usable I/O pads while maintaining smaller die sizes.
Solution Approach 2:
The packaging structure is segmented into distinct functional layers: the die, the package substrate, and the I/O pad array. By separating the I/O pad functionality from the die surface and relocating it to the package substrate, the system enables increased I/O pad density without constraining the die size.
2Quantity of substance
If the pitch of the pads is decreased to increase I/O pad density, then more I/O pads can be packed, but solder bridges may occur
Solution Approach 1:
By redistributing I/O pads onto the package substrate rather than confining them to the die surface, the patent increases the available area for pad placement. This allows maintenance of larger pad pitch on the substrate while achieving higher overall I/O pad density through the expanded footprint of the package substrate.
3Productivity
If fan-in packaging is used with smaller dies, then throughput is greater and cost is lower, but the number of I/O pads is limited
Solution Approach 1:
The patent performs I/O pad redistribution and routing operations during the wafer-level packaging process rather than requiring individual die processing. By establishing the fan-out I/O architecture in advance at the wafer level, the system achieves high I/O pad density while maintaining the throughput advantages of wafer-level processing.
4Ease of manufacture
If die-to-die metal connections are routed perpendicular to die edges, then routing is simpler, but stress increases during thermal cycling
Solution Approach 1:
The patent intentionally introduces asymmetry into the metal connection routing by angling the traces relative to the die edges rather than routing them perpendicular to the edges. This asymmetric routing pattern creates a more uniform stress distribution during thermal cycling, reducing the risk of connection failure while maintaining manufacturing feasibility.
Data Source
AI summary
Semiconductor devices and methods of forming are provided. A molding compound extends along sidewalls of a first die and a second die. A redistribution layer is formed over the first die, the second die, and the molding compound. The redistribution layer includes a conductor overlying a gap between the first die and the second die. The conductor is routed at a first angle over an edge of the first die. The first angle is measured with respect to a straight line that extends along a shortest between the first die and the second die, and the first angle is greater than 0.