Fan-out Line Routing for Reduced Non-display Area in Display Devices
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Solution Overview
Problem
The development of display devices with reduced manufacturing costs is hindered by the complexity and cost of data driving circuits, particularly in achieving bezel-less and infinity display designs with efficient fan-out line arrangements.
Innovation Solution
The display device incorporates a novel arrangement of fan-out lines in multiple layers, with bypass fan-out lines formed from a source metal layer different from the fan-out lines, allowing for a reduced size of the fan-out area and alignment of output terminals with data lines, thereby reducing development costs and improving display quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional fan-out line arrangements are used in data driving circuits, then the circuit can function properly, but the development cost increases and the non-display area size increases
Solution Approach 1:
The patent applies multi-layer routing by forming fan-out lines and bypass fan-out lines on different layers (first and second layers) of the substrate. This vertical dimensionality change allows lines to bypass each other without intersecting on the same plane, reducing the horizontal area required in the non-display region and simplifying the routing design.
Solution Approach 2:
The patent segments the fan-out line routing into two types: conventional fan-out lines and bypass fan-out lines. The bypass fan-out lines are specifically designed to route around complex areas (such as rounded corners of the display region) through the non-display area, while conventional fan-out lines handle standard routing. This segmentation allows optimized routing paths that reduce overall non-display area requirements.
2Adaptability or versatility
If fan-out lines are arranged to connect output terminals to data lines in complex display areas (e.g., rounded corners), then all data lines can be connected, but the fan-out area size increases
Solution Approach 1:
By utilizing multiple layers for fan-out line routing, the patent enables comprehensive connection coverage for all data lines including those in complex display areas with rounded corners, without proportionally increasing the horizontal fan-out area. The vertical layering provides additional routing space.
Solution Approach 2:
The bypass fan-out lines act as intermediary routing paths that connect output terminals to data lines in complex display areas by routing through the non-display area. These intermediary lines facilitate connections that would otherwise require larger direct routing paths.
3Area of stationary object
If multiple layers are used for fan-out lines, then the fan-out area size is reduced, but the manufacturing complexity increases
Solution Approach 1:
The patent employs exactly two layers for fan-out line routing, which provides sufficient vertical space to reduce the horizontal fan-out area while maintaining manufacturing feasibility. This moderate use of multi-layering balances area reduction benefits with manufacturing complexity constraints.
Data Source
AI summary
A display device includes a data driving circuit disposed in a non-display area and including output terminals for outputting a data voltage to the data-lines, a first fan-out line disposed in the non-display area and including a first end connected to an output terminal corresponding to a data line in a first-area of a display area and a second end connected to a first contact portion disposed in an area adjacent to an end of the data driving circuit, a second fan-out line disposed in the non-display-area and including a first end connected to an output terminal corresponding to a data-line in a second area of the display-area and a second end connected to the data-line in the second-area, and a bypass fan-out line disposed in the non-display area and the display area and including a first end connected to the first contact portion and a second end connected to the data-line in the first area.