Fan-Out Semiconductor Package Redistributing I/O Terminals
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Solution Overview
Problem
The existing fan-in semiconductor packages face challenges in accommodating a large number of I/O terminals and compact size requirements, as all I/O terminals need to be disposed inside the semiconductor chip, limiting their application and making it difficult to directly mount them on electronic device main boards.
Innovation Solution
A fan-out semiconductor package design that redistributes connection terminals outwardly of the semiconductor chip, using a first interconnection member with a through-hole, a semiconductor chip, an encapsulant, and a second interconnection member with a redistribution layer, along with a resin layer that planarizes protrusion bumps to facilitate fine pattern implementation and reduce spatial limitations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If all I/O terminals are disposed inside the semiconductor chip (fan-in package), then the chip can be compact, but it becomes difficult to accommodate a large number of I/O terminals and mount directly on main boards
Solution Approach 1:
The patent transitions from a two-dimensional arrangement of I/O terminals on the chip surface to a three-dimensional structure using multiple interconnection layers. The first and second interconnection members with redistribution layers are stacked vertically, allowing I/O terminals to be distributed across multiple layers and extended outwardly from the chip region, effectively increasing the available area for I/O terminals without increasing the chip footprint.
Solution Approach 2:
The patent employs a nested structure where the semiconductor chip is disposed within a through-hole of the first interconnection member, which is in turn disposed within the encapsulant. The second interconnection member is stacked on the first interconnection member, creating a nested arrangement of interconnection structures that allows for compact integration while extending functionality outwardly.
2Adaptability or versatility
If connection terminals are redistributed outwardly (fan-out package), then more I/O terminals can be accommodated, but the package size increases
Solution Approach 1:
The patent utilizes vertical stacking of the first and second interconnection members with their respective redistribution layers to accommodate more I/O terminals in the vertical dimension rather than expanding horizontally. This multi-layer approach allows I/O terminals to be distributed across different heights, reducing the footprint area while maintaining high I/O terminal capacity.
Solution Approach 2:
The patent divides the interconnection structure into multiple segments: the first interconnection member with its redistribution layer, the semiconductor chip, the encapsulant, and the second interconnection member with its redistribution layer. This segmentation allows each component to perform specific functions and be optimized independently, enabling compact integration while achieving fan-out functionality.
3Reliability
If protrusion bumps are used for connection, then electrical connection is achieved, but step portions create difficulty in implementing fine patterns
Solution Approach 1:
The patent applies a planarization process to the protrusion bumps before forming the second interconnection member. This preliminary action removes step portions and creates a flat surface, enabling subsequent fine pattern formation without manufacturing difficulties. The planarization is performed in advance to prevent interference with later patterning steps.
Data Source
AI summary
A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole, having an active surface having a connection pad disposed thereon and an inactive surface opposing the active surface, and having a protrusion bump disposed on the connection pad; an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip; and a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip. In the fan-out semiconductor package, step portions of the protrusion bumps may be removed.