Fan-Out Semiconductor Package With Redistribution Layer
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Solution Overview
Problem
Current semiconductor packaging technologies, such as fan-in packages, face challenges in accommodating semiconductor chips with a large number of I/O terminals or compact sizes due to spatial limitations and the need for redistribution of connection pads, making it difficult to directly mount these packages on electronic device main boards without using separate interposer substrates.
Innovation Solution
The fan-out semiconductor package design includes a first connection member with a through-hole, a semiconductor chip with a redistribution layer, and an encapsulant with a cavity exposing the inactive surface, allowing for the redistribution of connection pads outside the chip's boundaries, enabling direct mounting on a main board without an interposer substrate, and incorporating additional semiconductor chips and passive elements for enhanced integration and thermal performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a fan-in semiconductor package is used to accommodate chips with large number of I/O terminals, then the connection pads can be redistributed, but the package size and thickness increase
Solution Approach 1:
The patent transitions from a planar fan-in package structure to a three-dimensional fan-out package structure by redistributing connection pads vertically and laterally outside the chip footprint. The encapsulant with cavity creates a new spatial dimension for pad arrangement, allowing high I/O count without increasing package footprint area.
Solution Approach 2:
The package structure is segmented into distinct functional zones: the chip mounting region, the encapsulant with cavity for pad redistribution, and the external connection region. This segmentation allows independent optimization of chip area and connection pad area, resolving the contradiction between high I/O count and compact package size.
2Adaptability or versatility
If an interposer substrate is used for redistribution, then connection pads can be extended outwardly, but the package complexity and number of components increase
Solution Approach 1:
The patent merges the interposer substrate function directly into the encapsulant structure. The encapsulant with integrated cavity serves both as protective enclosure and as the redistribution platform, eliminating the need for a separate interposer substrate layer and reducing overall package complexity.
Solution Approach 2:
The encapsulant is designed with multi-functionality: it provides mechanical protection, electrical insulation, structural support, and serves as the redistribution layer platform. This universal design eliminates the need for dedicated interposer substrates, simplifying the package structure while maintaining pad redistribution capability.
3Quantity of substance
If multiple semiconductor chips are packaged simultaneously in a multichip package, then integration is enhanced, but the package thickness increases
Solution Approach 1:
The patent applies local quality by creating a cavity within the encapsulant that provides dedicated three-dimensional space for mounting multiple chips and passive elements. This localized void space allows vertical stacking and lateral arrangement of multiple components without uniformly increasing package thickness, as the cavity is strategically positioned to accommodate components while maintaining overall compact dimensions.
Data Source
AI summary
A fan-out semiconductor package includes a first connection member having a through-hole, a semiconductor chip disposed in the through-hole and including an active surface having connection pads disposed thereon and an inactive surface opposing the active surface, a second connection member disposed on the active surface of the semiconductor chip and including a redistribution layer electrically connected to the semiconductor chip, and an encapsulant encapsulating the semiconductor chip and having a cavity disposed above the inactive surface of the semiconductor chip.