Fan-Out SiP Redistribution Layer Area Expansion
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Solution Overview
Problem
Fan-out system-in-package (FOSiP) structures face challenges in yield and production time due to the formation of conductive pillars and encapsulant molding/grinding processes, which also limit the area of the redistribution layer, failing to meet the high input/output (I/O) requirements of certain products.
Innovation Solution
The electronic device incorporates a first and second wiring structure, with a high-density and low-density circuit pattern layer respectively, where the second electronic component is physically separated from the encapsulant and electrically connected to the conductive element, allowing for increased area for the redistribution layer without affecting the yield or production time of the semiconductor chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conductive pillars and encapsulant molding/grinding processes are used in FOSiP structures, then electrical connection between components is achieved, but yield and production time are adversely affected
Solution Approach 1:
The patent extracts the second electronic component from the encapsulant structure, allowing it to be disposed over the first electronic component without being enclosed by the encapsulant. This separation eliminates the need for complex molding and grinding processes while maintaining electrical connection through conductive elements, thereby improving yield and reducing production time.
Solution Approach 2:
The patent segments the package structure into distinct regions: the encapsulant encapsulates only the first electronic component and conductive elements, while the second electronic component is disposed separately over the first component. This segmentation allows independent processing of different components, simplifying manufacturing steps and improving productivity.
2Area of stationary object
If conventional FOSiP structures are used, then compact packaging is achieved, but the area of the redistribution layer is limited, failing to meet high I/O requirements
Solution Approach 1:
The patent utilizes the vertical dimension by disposing the second electronic component over the first electronic component in a stacked configuration. This three-dimensional arrangement increases the available area for the redistribution layer and I/O connections without increasing the horizontal footprint, thereby meeting high I/O requirements while maintaining compact packaging.
Data Source
AI summary
An electronic device includes a first electronic component, an encapsulant and a second electronic component. The encapsulant encapsulates the first electronic component. The second electronic component is disposed over the first electronic component and separated from the encapsulant. The second electronic component is configured to receive a power from the first electronic component.