Fan-out Semiconductor Package Stacked Chips Thickness Reduction
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Solution Overview
Problem
Conventional fan-out semiconductor packages face challenges in thickness reduction and signal loss due to the separate manufacturing and stacking of lower and upper packages, which limits their application in compact devices like SSDs.
Innovation Solution
A fan-out semiconductor package design that directly mounts DRAM and/or a controller on a lower package with redistribution layers, connecting them to wiring layers, and stacks NAND flash on an upper surface without an interposer, using connection conductors for electrical connection, thereby reducing thickness and signal transfer paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional POP type package structure is used with separate lower and upper packages, then manufacturing flexibility is improved, but package thickness increases and signal loss occurs
Solution Approach 1:
The patent merges the lower package (containing DRAM and controller) and upper package (containing NAND flash) into a single integrated fan-out semiconductor package. The connection member with redistribution layers is integrated within the same package structure, eliminating the need for separate package stacking. This consolidation reduces the overall package thickness while maintaining manufacturing flexibility through a unified fabrication process.
2Ease of manufacture
If conventional POP type package structure is used with separate lower and upper packages, then manufacturing flexibility is improved, but signal loss increases
Solution Approach 1:
The connection member with redistribution layers serves as an intermediary structure that provides optimized signal pathways between the DRAM/controller and NAND flash within the integrated package. This intermediary connection structure reduces signal loss by providing controlled impedance paths and minimizing via transitions compared to conventional stacked package approaches.
3Length of stationary object
If stack type NAND flash is directly mounted on lower package without interposer, then package thickness is reduced, but electrical connection complexity increases
Solution Approach 1:
The connection member performs self-service by providing integrated redistribution layers that automatically route signals between the stacked chips. The redistribution layers are formed as part of the connection member structure itself, eliminating the need for external interposers or complex wire bonding processes. This self-integrated approach reduces package thickness while managing electrical connection complexity through automated routing.
Data Source
AI summary
A fan-out semiconductor package includes a core member having a first through-hole and including wiring layers; a first semiconductor chip disposed in the first through-hole and having first connection pads formed on a lower side of the first semiconductor chip; a first encapsulant covering the core member and the first semiconductor chip; a connection member disposed below the core member and the first semiconductor chip and including redistribution layers; a first stack chip disposed on the first encapsulant and electrically connected to the wiring layers through a first connection conductor; and a second encapsulant disposed on the first encapsulant and covering the first stack chip. The first semiconductor chip includes DRAM and/or a controller, the first stack chip includes a stack type NAND flash, and the first connection pads of the first semiconductor chip are electrically connected to the wiring layers through the redistribution layers.