Fan-out semiconductor package with stacked core members
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Solution Overview
Problem
Current semiconductor packaging technologies, such as fan-in packages, face challenges in accommodating a large number of input/output terminals and achieving reliable mounting on electronic device mainboards due to spatial limitations and warpage issues, especially when multiple memory chips are stacked and interconnected via wire bonding.
Innovation Solution
The fan-out semiconductor package design includes a stack of semiconductor chips with core members and encapsulants, using vias to form signal paths instead of wire bonding, which allows for redistribution of connection pads outside the chip area, enhancing reliability and minimizing signal loss, and eliminates the need for an interposer substrate, thereby reducing thickness and preventing warpage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wire bonding is used to interconnect multiple memory chips, then electrical connection between chips is achieved, but signal loss increases and reliability decreases
Solution Approach 1:
The patent extracts the wire bonding process from the interconnection system and replaces it with direct pad-to-pad electrical connections through the stacked chip structure. This eliminates the intermediate wire bonding step that causes signal loss and reliability issues, while maintaining electrical connectivity between multiple memory chips.
Solution Approach 2:
The patent introduces an intermediary redistribution layer structure that facilitates direct electrical connection between pads of stacked chips without requiring wire bonding. This intermediary layer acts as a mediator to achieve reliable electrical connection while minimizing signal loss.
2Adaptability or versatility
If connection pads are redistributed outside the chip area, then spatial limitations are overcome and more I/O terminals are accommodated, but package complexity increases
Solution Approach 1:
The patent transitions from planar pad distribution to three-dimensional pad redistribution by stacking chips vertically. Connection pads are redistributed outside the original chip area through the vertical stacking dimension, allowing more I/O terminals to be accommodated without significantly increasing package complexity.
Solution Approach 2:
The patent segments the connection pad distribution across multiple stacked chip layers. Each chip in the stack contributes its own pads to the overall I/O capacity, effectively distributing the connection terminals across the vertical dimension and increasing total I/O capability.
3Adaptability or versatility
If multiple semiconductor chips are stacked to increase functionality, then system capability is enhanced, but warpage issues occur and reliability decreases
Solution Approach 1:
The patent applies local quality control by ensuring uniform material properties and structural characteristics at each chip interface in the stack. By maintaining consistent local quality across all bonding interfaces, the overall structural stability is improved and warpage is minimized while preserving enhanced system functionality.
Solution Approach 2:
The patent promotes homogeneity in the stacked chip structure by using matching materials and uniform bonding processes across all chip interfaces. This homogeneous construction reduces differential stress and thermal expansion that cause warpage, thereby maintaining structural stability while enabling multiple chips to be stacked for enhanced functionality.
Data Source
AI summary
A fan-out semiconductor package includes a first core member including a first through-hole, a first semiconductor chip disposed in the first through-hole of the first core member, a first encapsulant configured to encapsulate at least a portion of the first semiconductor chip, a first connection member disposed on the first semiconductor chip and including a first redistribution layer, a second core member adhered to a lower surface of the first connection member and including a second through-hole, a second semiconductor chip disposed in the second through-hole of the second core member, a second encapsulant configured to encapsulate the second semiconductor chip, the second core member, and the first connection member, a second connection member disposed on the second semiconductor chip and including a second redistribution layer, and a connection via penetrating through the second core member and configured to electrically connect the first redistribution layer and the second redistribution layer.