3D Fanout Stacking with Conductive Pillars and RDL
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor packaging technologies face challenges in integrating increasing I/O pads into smaller form factors while maintaining performance and reducing power consumption, particularly in mobile devices, where traditional wire bond technologies are inefficient for 3D stacking and fan out structures.
Innovation Solution
The implementation of a 3D semiconductor package with conductive pillars and a redistribution layer (RDL) that facilitates short communication paths between die, allowing for high routing densities and reduced z-height, using a fan out build up process with planarized stud surfaces or pre-formed conductive pillars and a single reconstituted carrier substrate, enabling efficient stacking and integration of multiple process nodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional wire bond packaging is used, then manufacturing process is simple, but routing density is low and z-height is large
Solution Approach 1:
The patent transitions from 2D wire bond routing to 3D vertical stacking with conductive pillars, enabling signals to route through the z-dimension. Multiple die are stacked vertically with TSVs providing through-silicon via connections, achieving high routing density while reducing overall package footprint and z-height compared to traditional wire bond PoP architectures.
Solution Approach 2:
The patent implements nested die stacking where active die are positioned within the footprint of larger I/O die. Smaller compute die are nested within the area of larger memory die, maximizing space utilization and achieving high routing density without increasing package area or z-height.
2Productivity
If more I/O pads are integrated into smaller form factor, then device performance increases, but power consumption increases and manufacturing complexity increases
Solution Approach 1:
The patent divides the package into multiple functional die stacked vertically, with each die having specialized functions (compute, memory, I/O). This segmentation allows independent optimization of each die and simplifies the overall packaging structure by eliminating the need for complex redistribution layers required in monolithic designs.
Solution Approach 2:
The patent introduces carrier substrates as intermediary elements that provide mechanical support and electrical interconnection between stacked die. The carrier substrate with embedded conductive vias acts as a mediator, simplifying the bonding process and reducing manufacturing complexity compared to direct die-to-die stacking.
3Productivity
If conductive pillars with RDL are used for 3D stacking, then routing density increases and z-height reduces, but manufacturing process complexity increases
Solution Approach 1:
The patent forms conductive pillars and RDL structures on die before stacking, allowing these complex features to be manufactured using standard semiconductor fabrication processes. This preliminary action enables high routing density to be achieved through batch processing rather than complex post-bonding operations.
Solution Approach 2:
The patent designs the stacking architecture so that each die level serves its own routing needs through integrated RDL and conductive pillar structures. The self-contained nature of each stack level simplifies manufacturing by eliminating the need for complex cross-level routing operations.
Data Source
AI summary
Semiconductor packages and fan out die stacking processes are described. In an embodiment, a package includes a first level die and a row of conductive pillars protruding from a front side of the first level die. A second level active die is attached to the front side of the first level die, and a redistribution layer (RDL) is formed on an in electrical contact with the row of conductive pillars and a front side of the second level active die.