Fan-out trace orientation for slim display borders
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Solution Overview
Problem
High-resolution display panels face challenges in achieving a slim border and effective sealant curing due to numerous fan-out traces, which also lead to high parasitic capacitance and reduced light coverage for sealant curing.
Innovation Solution
The pixel array substrate design includes a substrate with distinct areas for signal lines and a driving element, where fan-out traces are arranged in overlapping groups with different angles and conductive layers, allowing for a slim border and improved sealant curing by minimizing parasitic capacitance and optimizing light exposure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If numerous fan-out traces are used to connect high-resolution signal lines to the driving element, then electrical connectivity is improved, but the border width cannot be reduced and parasitic capacitance increases
Solution Approach 1:
The patent applies dimensionality change by transitioning fan-out traces from a single-layer planar arrangement to a multi-layer three-dimensional structure. Traces are distributed across multiple conductive layers with vertical stacking, allowing signals to fan out in both horizontal and vertical dimensions. This reduces the horizontal border width requirement while maintaining electrical connectivity for high-resolution displays.
Solution Approach 2:
The patent segments the fan-out trace structure into multiple conductive layers, with each layer containing a subset of traces. This segmentation allows traces to be organized in discrete layers rather than a single crowded plane, reducing parasitic capacitance between adjacent traces while maintaining connectivity to all signal lines.
2Reliability
If numerous fan-out traces are used to connect signal lines, then electrical connectivity is improved, but parasitic capacitance increases
Solution Approach 1:
By distributing traces across multiple vertical layers, the patent increases the vertical separation between traces that would otherwise be adjacent in a single layer. This three-dimensional arrangement reduces parasitic capacitance between traces while maintaining electrical connectivity to all signal lines in the high-resolution display.
Solution Approach 2:
Segmenting traces into multiple conductive layers reduces the density of traces in any single layer, thereby reducing the parasitic capacitance between adjacent traces. Each layer contains a manageable subset of traces, reducing overall parasitic effects while maintaining complete electrical connectivity.
3Reliability
If numerous fan-out traces are used, then signal connectivity is improved, but light coverage for sealant curing is reduced
Solution Approach 1:
The patent moves fan-out traces from a single-planar arrangement to a multi-layer three-dimensional structure. This vertical stacking allows light to cure sealant in the planar region more effectively, as traces are distributed across multiple layers rather than forming a dense single-layer barrier. The multi-layer configuration reduces light blocking while maintaining signal connectivity.
Data Source
AI summary
A pixel array substrate includes signal lines arranged in an arranging direction, pixel structures electrically connected to the signal lines, a driving element and fan-out traces. Each of the fan-out traces is electrically connected to one of the signal lines and the driving element. A fan-out trace group includes a first fan-out trace and a second fan-out trace. A main portion of the first fan-out trace extends in a first direction, and the first direction and the arranging direction have a first angle α therebetween. A main portion of the second fan-out trace extends in a second direction, and the second direction and the arranging direction have a second angle β therebetween. The first angle α is different from the second angle β. In addition, another pixel array substrate has also been proposed.