Fanout Tree Current Stabilization via Data Scrambling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing time division multiplexed (TDM) memory switches face challenges in managing large variations in power supply current demands, leading to inefficiencies and increased complexity in power supply systems due to high parasitic capacitance and current spikes during data transmission.
Innovation Solution
The implementation of a data transmission apparatus that splits the fanout tree into sub-groups with equal parasitic capacitance and scrambles the data using specific scrambling sequences to maintain a constant number of toggled bits over time, thereby stabilizing current demand and reducing voltage spikes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is transmitted through a large fanout tree in a TDM memory switch, then aggregate throughput is increased, but current demand variations and voltage spikes increase due to high parasitic capacitance
Solution Approach 1:
The patent segments the data transmission process by dividing the fanout tree into multiple sub-trees and separating data into multiple groups. Each group is transmitted through a dedicated sub-tree, which reduces the capacitance load on any single transmission path and enables better control of current demand variations while maintaining high aggregate throughput.
Solution Approach 2:
The patent implements periodic transmission of different data groups through different sub-trees in a cyclic manner. This periodic action allows the system to distribute the capacitive loading over time, reducing peak current demands and voltage spikes while maintaining continuous high throughput across all fanout nodes.
2Object-generated harmful factors
If the fanout tree is divided into sub-trees with equal parasitic capacitance, then current demand variations are reduced, but device complexity increases due to additional grouping and scrambling logic
Solution Approach 1:
The patent segments the data transmission process by dividing the fanout tree into multiple sub-trees and separating data into multiple groups. Each group is transmitted through a dedicated sub-tree, which reduces the capacitance load on any single transmission path and enables better control of current demand variations while maintaining high aggregate throughput.
Solution Approach 2:
The patent applies scrambling operations that systematically change the bit patterns of data groups. By controlling the number of toggled bits through scrambling, the patent equalizes the capacitive loading effects across different transmission paths, reducing current demand variations without requiring complex dynamic adjustment mechanisms.
3Object-generated harmful factors
If scrambling sequences are applied to maintain constant toggled bits, then voltage spikes are minimized, but manufacturing precision requirements increase for implementing accurate scrambling sequences
Solution Approach 1:
The patent applies scrambling operations that systematically change the bit patterns of data groups. By controlling the number of toggled bits through scrambling, the patent equalizes the capacitive loading effects across different transmission paths, reducing current demand variations without requiring complex dynamic adjustment mechanisms.
Solution Approach 2:
The patent uses predetermined scrambling sequences that can be implemented through copying and replicating established bit pattern transformations. These sequences are designed to maintain a constant number of toggled bits, which minimizes voltage spikes while using straightforward implementation logic that reduces manufacturing precision requirements.
Data Source
AI summary
A method and apparatus are provided for reducing current demand variations in large fanout trees. The fanout tree is split into at least 2 sub-groups, each preferably with substantially equal parasitic capacitance. Data is then scrambled according to a scrambling sequence function to provide scrambled data having a constant number of bits that are toggled with respect to time, such as when observed in pairs of sub-groups. Functionally, an apparatus according to an embodiment of the present invention includes 3 blocks: a scrambler, egress logic, and a de-scrambler. The egress logic is simply a block of storage that can reorder the bytes received from the scrambler. The de-scrambler de-scrambles the retransmitted data based on the scrambling sequence function. Embodiments of the present invention can be applied to any system where data must fanout from a single source to many destinations, such as switches.