Fan-Out Package Vertical Interconnects via Additive Electroplating
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Solution Overview
Problem
The adoption of fan-out panel level processing (FOPLP) for manufacturing vertical interconnects in discrete power devices is hindered by slow and costly subtractive processes, limited via aspect ratio, and size constraints due to laser drilling and photolithography.
Innovation Solution
A method involving a patterned seed layer of electrically conductive material on a substrate, followed by a dielectric layer with vertical passages, filled with additional conductive material through electroplating, ensuring precise and efficient vertical interconnects, and allowing for integrated component packaging and seamless electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If subtractive processes are used for generating vias, then manufacturing is possible, but the process is slow and costly
Solution Approach 1:
The patent inverts the conventional subtractive via formation process by using an additive approach. Instead of removing material to create vias, the invention forms vias by selectively depositing conductive material in desired locations through electroplating, thereby eliminating the slow and costly subtractive processes while significantly improving manufacturing speed and efficiency.
Solution Approach 2:
The patent replaces the mechanical subtractive processes (laser drilling, mechanical milling) with an electrochemical deposition process. By using electroplating to form conductive vias, the invention eliminates the limitations of mechanical methods and achieves faster, more cost-effective via formation with better precision and uniformity.
2Manufacturing precision
If laser drilling and photolithography are used for via formation, then via creation is possible, but the aspect ratio and size are limited
Solution Approach 1:
The patent changes the fundamental parameters of via formation by transitioning from optical and mechanical methods to electrochemical deposition. This enables precise control of via dimensions and aspect ratios that were previously unachievable with laser drilling and photolithography, while providing greater design flexibility for complex interconnect structures.
Solution Approach 2:
The patent replaces the optical and mechanical via formation methods with electrochemical deposition, thereby overcoming the inherent limitations of laser drilling and photolithography in achieving high aspect ratios and precise dimensional control. The electroplating process naturally conforms to the substrate topology and can create vias with superior aspect ratios and uniformity.
3Manufacturing precision
If patterned seed layer and electroplating are used, then high-quality uniform deposition is achieved, but additional process steps are required
Solution Approach 1:
The patent applies preliminary action by forming a patterned seed layer before the electroplating process. This seed layer serves as a foundation that ensures uniform and controlled deposition of conductive material during electroplating, achieving high-quality via formation with precise dimensional control and excellent uniformity throughout the via structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances manufacturing efficiency, achieves high-quality and uniform deposition of conductive material, and creates robust electrical pathways, facilitating versatile circuit architectures and reliable interfacing with external systems.
Implementation Method 1
Additional electrically conductive material is grown onto the exposed area of the seed layer, filling an inside of the vertical passage with the additional electrically conductive material to form a vertical interconnect
Data Source
Figure 1A~1D
Figure 2A~2D
Figure 3A~3D
AI summary
A method of manufacturing an electronic stack (10). A substrate (S) is provided with a first seed layer (11). A first dielectric layer (12) is provided at least partially covering the first seed layer (11). At least one vertical passage is formed through the first dielectric layer (12) to leave a respective exposed area of the first seed layer (11) free of the electrically insulating material. Additional electrically conductive material (11n) is grown onto the exposed area of the first seed layer (11), filling an inside of the vertical passage with the additional electrically conductive material (11n) to form a vertical interconnect (V) of the electronic stack (10) through the first dielectric layer (12). The electronic stack (10) may be diced to form a fan-out panel package. An electronic component (1) may be arranged as part of the electronic stack (10) to form a fan-out package.