Fan-Out Package Via Layout for Thermal Stress Reliability
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Solution Overview
Problem
Fan-out semiconductor packages face reliability issues due to stress concentrations on connection terminals and vias, particularly from thermal expansion differences between semiconductor chips and main boards, leading to potential delamination and cracking.
Innovation Solution
The design includes a first and second interconnection member with redistribution layers, where the first via is positioned within the inner region of the connection terminal pad and the second via in the outer region, reducing stress concentrations and improving reliability by forming electrical pathways that alleviate stress at critical areas.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If connection terminals are redistributed outwardly to achieve compact package size, then package size is reduced, but stress concentration on vias and connection terminals increases
Solution Approach 1:
The patent applies local quality by differentiating the positioning of vias based on their location within the connection terminal pad. First vias are positioned in the inner region where stress is lower, while second vias are positioned in the outer region where stress is higher. This localized differentiation allows the package to maintain compact size while addressing stress concentration issues at specific critical locations.
Solution Approach 2:
The connection terminal pad is segmented into an inner region and an outer region for the purpose of via placement. By dividing the pad area into these functional zones and placing vias differently in each zone, the patent optimizes stress distribution while maintaining the fan-out package's compact form factor.
2Ease of manufacture
If vias are positioned centrally in connection terminal pads to simplify manufacturing, then manufacturing complexity is reduced, but stress concentration and delamination risk increase
Solution Approach 1:
Instead of uniformly positioning all vias at the center for manufacturing simplicity, the patent applies local quality by positioning first vias in the inner region and second vias in the outer region of connection terminal pads. This differentiated approach targets stress concentration issues at specific locations while maintaining manufacturability.
Solution Approach 2:
The patent converts the potentially harmful stress concentration effect into a beneficial design parameter by intentionally positioning second vias in the outer region where they can serve as stress relief structures. What would normally be considered a problematic area (outer region with higher stress) is transformed into a functional zone for placing vias that actively manage stress distribution.
3Reliability
If multiple vias are placed in outer region to reduce stress, then via reliability improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent defines specific regional zones (inner region and outer region) within connection terminal pads, providing clear manufacturing guidelines for via placement. This regional differentiation simplifies the manufacturing process by establishing standardized placement zones rather than requiring precise individual positioning of each via, thereby maintaining reliability while managing manufacturing precision requirements.
Data Source
AI summary
A fan-out semiconductor package includes connection pads of a semiconductor chip that are redistributed and electrically connected to connection terminals by an interconnection member. In the fan-out semiconductor package, disposition forms of vias and pads in the interconnection member are designed so that stress may be reduced, such that reliability is improved.