Fan-Out Package Via Offset Layout for Dense Reliable Interconnects
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Solution Overview
Problem
Semiconductor packages face challenges in increasing the number of external connection terminals while maintaining reliability and reducing manufacturing costs, as existing fan-out packages struggle with peeling and open/short circuit failures due to the accumulation of curved and stepped portions in the via arrays and pads.
Innovation Solution
The semiconductor package incorporates a redistribution layer with offset via arrays and pads, where the second via array is positioned above the first via array without overlapping, and a redistribution pattern is used to prevent peeling and open/short circuit failures by maintaining a specific offset distance and using conductive materials with barrier layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of external connection terminals is increased, then the connection capability is improved, but the planar area of the semiconductor package increases
Solution Approach 1:
The patent transitions from a two-dimensional planar arrangement of connection terminals to a three-dimensional stacked via array configuration. Multiple via arrays are arranged vertically at different heights, allowing the package to accommodate more external connection terminals without increasing the footprint area. The via arrays extend in the vertical direction (third direction) rather than only in the horizontal plane.
2Quantity of substance
If via arrays and pads are densely arranged to increase connection terminals, then the connection density is improved, but peeling and open/short circuit failures occur
Solution Approach 1:
The patent divides the via structure into multiple separate via arrays positioned at different vertical levels and horizontal positions. Each via array is spaced apart from others, preventing the accumulation of stress and curvature that causes peeling. The segmentation of via arrays into first, second, and third arrays at different heights reduces the density of curved portions at any single location, thereby improving reliability.
Solution Approach 2:
The via arrays are arranged asymmetrically in the vertical direction with different spacing and positioning. The first via array is at a first height, the second via array at a second height, and the third via array at a third height, creating an asymmetric distribution that prevents uniform stress accumulation. This asymmetric arrangement disrupts the pattern that would otherwise lead to systematic peeling failures.
3Area of stationary object
If multiple via arrays are stacked vertically to increase connection terminals, then the planar area is reduced, but curved and stepped portions accumulate causing reliability issues
Solution Approach 1:
The patent utilizes the vertical dimension (third direction) to distribute via arrays at different heights instead of concentrating them in a single plane. The first via array is positioned at a first vertical level, the second via array at a second vertical level, and the third via array at a third vertical level. This vertical distribution reduces the accumulation of curved and stepped portions at any single horizontal location, maintaining reliability while achieving high connection density in a compact planar footprint.
Data Source
AI summary
Provided is a semiconductor package including a semiconductor chip, a connection structure below the semiconductor chip and electrically connected to the semiconductor chip, and an external connection terminal below the connection structure, wherein the connection structure includes a first via array including a plurality of first vias in a first direction, a second via array above the first via array and including a plurality of second vias in the first direction, and a first pad between the first via array and the second via array and on upper surfaces of the plurality of the first vias, wherein the second via array is offset from the first via array in the first direction and does not overlap the first via array in a vertical direction.