Fan-Out Wafer Level Package for High-Capacity Semiconductor Stacking
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Solution Overview
Problem
The challenge lies in packaging high-capacity semiconductor chips without increasing the overall thickness of the package, particularly for WIO2 mobile DRAM memory chips, where applying TSV technology is difficult, limiting the stacking of high-capacity and high-speed semiconductor devices in small electronic products.
Innovation Solution
A package-on-package type semiconductor device is realized using a fan-out wafer level package technology, where an SoC package is stacked under and over a fan-out package structure, embedding WIO2 mobile DRAM memory chips without TSV technology, allowing for easy stacking of driving and external memory packages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If TSV technology is applied to package high-capacity semiconductor chips, then the capacity and speed of the device are improved, but the overall thickness of the package increases
Solution Approach 1:
The patent transitions from vertical stacking (TSV technology increasing thickness) to lateral expansion through fan-out structure, where semiconductor chips are arranged in a planar configuration with extended signal paths. This dimensional change allows high-capacity packaging without proportionally increasing package thickness.
Solution Approach 2:
The package is divided into multiple functional regions including die pad, fan-out region with redistribution layers, and external connection terminals. This segmentation allows independent optimization of each region, enabling high-capacity chip integration while controlling overall package dimensions through distributed signal routing.
2Speed
If TSV technology is used for stacking semiconductor chips, then high-speed operation is achieved, but the manufacturing complexity increases
Solution Approach 1:
The patent extracts the through-silicon via formation step from the manufacturing process, replacing it with fan-out technology that uses surface-mounted connections and redistribution layers. This extraction eliminates the complex TSV fabrication steps while maintaining high-speed signal transmission through optimized lateral routing paths.
Solution Approach 2:
The fan-out structure serves multiple functions simultaneously: it provides signal redistribution, mechanical support, thermal management pathways, and electrical connections. This multi-functionality replaces the specialized TSV structure, simplifying the overall manufacturing process while achieving comparable or superior performance.
3Quantity of substance
If multiple semiconductor chips are mounted in a limited space, then the capacity of the electronic product is improved, but the mounting difficulty increases
Solution Approach 1:
The patent merges multiple chip functions into a single fan-out package structure, where multiple semiconductor chips are integrated within one package footprint. The combined structure uses shared redistribution layers and common mounting interfaces, reducing the number of discrete mounting operations while increasing total chip capacity.
Solution Approach 2:
The fan-out redistribution layers act as intermediaries between multiple semiconductor chips and external connections. These intermediary structures provide standardized connection points that simplify the mounting process, allowing multiple chips to be integrated systematically rather than requiring complex individual wire bonds or TSV alignments.
Data Source
AI summary
A semiconductor device may include a bottom package embedded with a first semiconductor chip. The semiconductor device may include a middle package stacked over the bottom package, and embedded with at least two second semiconductor chips in a fan-out structure. The semiconductor device may include a top package stacked over the middle package, and embedded with at least two third semiconductor chips.