High Fanout Signal Optimization via Window Partitioning

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Solution Overview

Problem

Conventional Electronic Design Automation (EDA) tools face difficulties in processing high fanout signals during physical synthesis of integrated circuits, leading to failures in meeting timing requirements due to inaccurate estimation of signal propagation delays.

Innovation Solution

The method involves assigning high fanout signal load pins into multiple windows based on their locations, replicating the source signal within each window, and connecting it to the associated load pins, with the source placed at the center of gravity or using a selected source location technique to optimize fanout distribution.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional EDA tools process high fanout signals using traditional methods, then the implementation process is simple, but the timing requirements cannot be met due to inaccurate delay estimation

Engineering Contradiction:

Improvetiming requirement satisfactionVSAvoidsignal processing complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent divides the target device into multiple windows and partitions high fanout load pins into different windows based on their locations. By replicating sources in each window and connecting them to local load pins, the signal processing is segmented into manageable regional units, improving delay estimation accuracy and timing requirement satisfaction.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent applies different processing strategies to different regions by creating window-specific source replicas. Each window receives customized source placement and connection optimization based on its specific load pin distribution, enabling localized quality improvement in delay estimation and timing analysis for high fanout signals.

Inventive Principle:

Principle #3Local quality

2Measurement precision

If the source is replicated in multiple windows, then the signal propagation delay estimation accuracy is improved, but the device resource usage increases

Engineering Contradiction:

Improvesignal propagation delay estimation accuracyVSAvoidnumber of source replicas

Core Design Contradiction:

Measurement precisionVSQuantity of substance

Solution Approach 1:

The patent segments the high fanout signal processing into multiple window-based regions, with each window containing a replicated source. This segmentation enables accurate delay estimation within each local region while managing the overall quantity of replicas through systematic window partitioning and load pin assignment.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent replicates sources in selected windows based on the distribution of load pins, rather than uniformly across the entire device. This partial replication approach provides sufficient delay estimation accuracy for high fanout signals while avoiding excessive resource consumption in regions where replication is not necessary.

Inventive Principle:

Principle #16Partial or excessive action

Data Source

PatentUS7853914B1Fanout-optimization during physical synthesis for placed circuit designs

Publication Date: 2010.12.14 XILINX INC

AI summary

A method of implementing a circuit design for a target device can include assigning load pins of a high fanout signal of a placed circuit design into a plurality of windows according to a location of each load pin on the target device. A source of the high fanout signal can be replicated, wherein each window is associated with a source of the high fanout signal. For each source of the high fanout signal, the source can be connected to load pins of the window associated with the source and the source can be placed within the window associated with the source. The placed circuit design can be output.