High-Density SRAM Bit-Line Pre-Charge for Far-End Timing
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Solution Overview
Problem
The increased resistance in bit lines (BLs) and the augmented number of cells per BL in advanced technology nodes lead to excessive pre-charge times at the far end of the bit lines, causing voltage disparities and functional issues during memory operations, particularly in SRAM systems.
Innovation Solution
Implementing far-end bit line pre-charge circuits that include equalizers to pre-charge bit lines and their complements equally, minimizing pre-charge time and preventing voltage disparities, thereby enhancing memory density and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of cells per bit line is increased to improve memory density, then memory density is improved, but the pre-charge time at the far end of bit lines becomes excessive
Solution Approach 1:
The patent divides the bit line into segments by placing pre-charge circuits at both the near end and far end of the bit line. This segmentation allows independent pre-charging of different portions, enabling the far end to be pre-charged without waiting for the entire bit line to charge from a single point, thus reducing pre-charge time while maintaining high memory density.
Solution Approach 2:
The pre-charge circuits perform preliminary action by pre-charging the bit lines to a predetermined voltage level before memory access operations. This preliminary pre-charging ensures that the bit lines are ready for rapid data access, eliminating the need for lengthy pre-charge periods during normal operations and thereby reducing the effective pre-charge time impact on overall system performance.
2Reliability
If the pre-charge time is extended to ensure proper charging of far-end bit lines, then voltage stability is improved, but memory operation speed deteriorates
Solution Approach 1:
By segmenting the bit line pre-charging into near-end and far-end operations with separate control circuits, the patent ensures that the far end receives adequate charging voltage for reliability while the segmented structure allows faster overall operation compared to a single long pre-charge cycle, thus maintaining both voltage stability and memory operation speed.
Solution Approach 2:
The patent changes the voltage parameter dynamically by using control circuits that can set different pre-charge voltage levels and timing for near-end and far-end bit lines. This parameter adjustment allows optimization of voltage stability for the far end while maintaining faster operation speeds overall, resolving the contradiction between reliability and speed.
3Device complexity
If traditional pre-charge circuits are used without far-end pre-charge, then device complexity is reduced, but voltage disparities occur causing functional issues
Solution Approach 1:
The patent adds segmentation by introducing far-end pre-charge circuits that divide the pre-charge function into multiple locations. While this increases device complexity, it eliminates voltage disparities and functional issues by ensuring proper voltage levels at the far end of bit lines, thus achieving the necessary reliability for correct memory operations.
Solution Approach 2:
The far-end pre-charge circuits act as intermediaries between the bit line and the memory cells at the far end. These intermediary circuits ensure that voltage disparities are eliminated and functional correctness is maintained, justifying the increased complexity by providing the necessary reliability for proper memory operation.
Data Source
AI summary
A memory circuit includes a memory array comprising a first portion comprising a plurality of first memory cells, and a second portion comprising a plurality of second memory cells. The memory circuit includes an input/output (I/O) circuit physically disposed next to the memory array along a first lateral direction. The I/O circuit is operatively coupled to the first portion and the second portion through a first access line and a second access line, respectively. The memory circuit includes a first pre-charge circuit physically disposed opposite the first portion from the I/O circuit, and configured to charge the first access line prior to accessing the first memory cells. The memory circuit includes a second pre-charge circuit physically disposed opposite the second portion from the first pre-charge circuit, and configured to charge at least a portion of the second access line prior to accessing the second memory cells.