Farrow Fractional Delay Filtering for Parallel Radar Data Streams
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Solution Overview
Problem
Digital signal processing systems used for simulating radar environments face distortion issues due to high radar bandwidths, which result in reduced accuracy of radar tests. Conventional computing devices are unable to filter out distortion in real-time or close-to-real-time due to the difference between sampling frequency and clock rate.
Innovation Solution
A processing element is implemented in the digital signal processing system, configured to receive time-ordered digital values from parallel data streams, store digital values, and apply a Farrow structured fractional delay filter to produce filtered digital values. This enables filtering even when the processing element's clock rate is slower than the sample rate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional filtering methods are used with a processing element operating at a lower clock rate than the sample rate, then device complexity is reduced, but the filtering accuracy and real-time performance deteriorate
Solution Approach 1:
The patent divides the high-speed sampling data stream into multiple parallel data streams, each processed by a separate processing element operating at a lower clock rate. This segmentation allows the system to maintain high effective processing throughput while using simpler, lower-frequency processing elements, resolving the contradiction between device complexity and filtering accuracy.
2Measurement precision
If the sampling frequency is increased to match the radar bandwidth, then measurement precision is improved, but the clock rate mismatch with conventional processing devices worsens, reducing productivity
Solution Approach 1:
The patent segments the high-frequency sampling task across multiple parallel processing elements operating at lower clock rates. By dividing the data stream and processing it in parallel, the system achieves real-time filtering capability matching the high sampling frequency without requiring individual processing elements to operate at prohibitively high clock rates.
Solution Approach 2:
The patent transitions from a single-dimensional sequential processing approach to a multi-dimensional parallel processing architecture. By introducing the dimension of parallelism, the system achieves high effective throughput through multiple lower-speed processors working simultaneously, resolving the productivity limitation of conventional single-processor approaches.
3Speed
If a single processing element operates at high clock rate to match sample rate, then filtering speed is improved, but device complexity and cost increase
Solution Approach 1:
The patent segments the high-speed processing requirement across multiple parallel processing elements operating at lower clock rates. This segmentation achieves the same effective processing speed as a single high-clock-rate processor while using simpler, lower-cost components, thereby resolving the contradiction between filtering speed and device complexity.
Data Source
AI summary
A processing element for implementation in a digital signal processing system is provided. The processing element is configured to receive a first data stream comprising a plurality of digital values where each value represents a sample of an analog signal. The processing element is further configured to receive a second data stream comprising a series of digital values where each value represents a sample of the analog signal. The processing element is configured to filter the first data stream via a first Farrow-structured fractional delay (FD) filter and output a filtered first data stream; filter the second data stream via a second Farrow-structured FD filter and output a filtered second data stream; and temporarily store values from the second data stream and output the stored values to the first Farrow-structured FD filter so that the stored values can be used to filter the first data stream.