Fast Address Decoder for Memory Array Access
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Solution Overview
Problem
Traditional processors experience load latency due to the two-cycle process of adding base and offset addresses to access memory, which delays the use of load operation results.
Innovation Solution
A system and method that uses a fast address decoder to initiate memory access by directly utilizing corresponding bits from operands to generate PGZO values, allowing for simultaneous decoding of sum with and without a carry, thereby reducing the time required to determine the proper memory entry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If traditional base+offset addition is used to compute effective address, then address computation is performed sequentially, but memory access time increases due to load latency
Solution Approach 1:
The patent performs preliminary decoding of address bits into PGZO values before the complete address sum is available. By pre-computing decoded values from partial address information and storing them in buffers, the system prepares memory access data in advance, allowing the memory access to proceed without waiting for the full address calculation to complete.
Solution Approach 2:
The patent segments the address computation process into independent parallel paths: one path computes the address sum through addition, while another path simultaneously decodes address bits into PGZO values. This segmentation allows both operations to proceed concurrently rather than sequentially, eliminating the load latency bottleneck.
2Reliability
If two-cycle addition process is used for base and offset addresses, then address computation is accurate, but memory access is delayed until both cycles complete
Solution Approach 1:
The system performs preliminary decoding of address bits into PGZO values before the addition cycle completes. By pre-computing and buffering decoded values from the first cycle, the memory access can initiate in the second cycle without re-computing decoded values, maintaining accuracy while improving speed.
Solution Approach 2:
The patent maintains continuous useful action by overlapping the decoding operation with the addition operation. While the addition is completing its second cycle, the decoded PGZO values are already available in buffers, ensuring no idle time occurs and the memory access proceeds continuously without interruption.
3Device complexity
If sequential address computation is performed, then circuit complexity is reduced, but load latency increases causing performance degradation
Solution Approach 1:
The patent segments the address handling into separate functional blocks: address bit extraction units, PGZO decoding units, and buffer storage units. Each segment performs a simple, dedicated function that can be implemented with minimal circuitry, yet the combined parallel operation achieves high performance without complex interdependencies.
Solution Approach 2:
The patent introduces buffer memory as an intermediary between the address computation and memory access stages. This intermediary stores pre-decoded PGZO values, allowing the memory access stage to retrieve ready-made data without waiting for computation to complete, thereby improving performance without requiring complex real-time computation circuits.
Data Source
AI summary
A method includes storing a first transaction entry to a first software configurable storage location, storing a second transaction entry to a second software configurable storage location, determining that a first transaction indicated by the first transaction entry has occurred, determining that a second transaction indicated by the second transaction entry has occurred subsequent to the first transaction, and, in response to determining that the first transaction occurred and the second transaction occurred, storing at least one transaction attribute captured during at least one clock cycle subsequent to the second transaction. The first and second software configurable storage locations may be located in a trace buffer, where the at least one transaction attribute is stored to the trace buffer and overwrites the first and second transaction attributes. Each transaction entry may include a dead cycle field, a consecutive transaction requirement field, and a last entry field.