Fast Bias Contour Model for Lithography Hot Spot Detection
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Solution Overview
Problem
Current design flows for integrated circuit (IC) manufacturing, which rely on DRC checking and OPC techniques, are inefficient and time-consuming due to the extensive simulations required for lithography process checks, leading to bottlenecks in identifying 'hot spots' and delaying IC design completion.
Innovation Solution
The implementation of a fast-bias contour (FBC) model that approximates OPC processes without generating OPC polygons or performing OPC steps, allowing for quick identification of errors and simulation results, thereby reducing simulation time and data size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If extensive simulations are performed for lithography process checks, then accuracy of hot spot identification is improved, but simulation time increases
Solution Approach 1:
The patent segments the lithography process check into two distinct stages: a fast preliminary check using simplified models to identify obvious hot spots, followed by a more accurate but time-consuming simulation only for cases that fail the preliminary check. This segmentation allows the system to maintain high accuracy for critical cases while dramatically reducing overall simulation time by avoiding extensive simulations for cases that would pass anyway.
Solution Approach 2:
The patent applies partial action by performing only the necessary level of simulation for each case. Instead of always running extensive simulations, the system performs a lightweight preliminary analysis first, and only applies the full extensive simulation when truly needed (when the preliminary check indicates a potential hot spot). This ensures accuracy is maintained for critical cases while avoiding wasted computational resources on cases that don't require it.
2Reliability
If DRC checking and OPC techniques are used, then lithography process compliance is verified, but design flow efficiency decreases
Solution Approach 1:
The patent applies preliminary action by implementing a fast preliminary lithography check that performs essential compliance verification before committing to time-consuming OPC and extensive simulation. This preliminary check uses simplified models and algorithms to quickly identify cases that are likely to fail, allowing the system to flag these for further review while letting clearly-passing cases proceed without the full OPC process, thereby maintaining reliability while improving overall design flow efficiency.
Data Source
AI summary
Integrated circuit design techniques are disclosed. In some methods, a target layout design having a geometric pattern thereon is received. A set of fast-bias contour (FBC) rules is applied to the target layout design to provide an electronic photomask having FBC-edits. The FBC-edits differentiate the electronic photomask from the target layout design, and the FBC rules are applied without previously applying optical proximity correction (OPC) to the target layout design. A lithography process check is performed on the electronic photomask to determine whether a patterned integrated circuit layer, which is to be manufactured based on the electronic photomask, is expected to be in conformance with the geometric pattern of the target layout design.