Fast-Bypass Memory Circuit for Shorter Data-to-Output Lag
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High-speed digital microarchitectures in integrated circuits are limited by data-to-output lag (tDQ) due to long data-setup time (tS) and clock-to-output lag (tCQ) in memory circuits, which can lead to logic errors from clock skew, jitter, and within-die delay variations, and traditional time-borrowing methods are not applicable to all memory circuits.
Innovation Solution
A non-transparent, fast-bypass memory circuit design that includes a D-type flip-flop with selection logic and upstream/downstream memory logic, utilizing a clocked sense-amplifier latch and unclocked RS latch to achieve short tS and tCQ, and is amenable to time borrowing, allowing for efficient clock speed extension and error reduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If traditional memory circuits are used, then data storage function is provided, but data-to-output lag (tDQ) is long due to long data-setup time (tS) and clock-to-output lag (tCQ)
Solution Approach 1:
The memory circuit is segmented into two parallel paths: a fast bypass path that provides direct data transmission with minimal delay, and a traditional storage path that ensures data stability. The selection logic dynamically chooses between these paths, allowing the circuit to achieve short tDQ when speed is critical while maintaining data integrity requirements.
Solution Approach 2:
The circuit employs dynamic path selection based on timing requirements. The selection logic adapts the data transmission path in real-time, switching between the fast bypass path (for speed-critical operations) and the traditional storage path (for stability-critical operations), thereby optimizing the balance between data-to-output lag and data throughput.
2Productivity
If clock speed is increased to improve data throughput, then productivity increases, but logic errors increase due to clock skew, jitter, and within-die delay variations
Solution Approach 1:
The selection logic acts as an intermediary that decouples the relationship between clock speed and data transmission reliability. By providing an alternative fast bypass path that is less sensitive to clock timing variations, the circuit can operate at higher clock speeds without proportionally increasing logic errors, as the selection logic routes data through the appropriate path based on timing conditions.
3Reliability
If time borrowing is implemented to absorb clock skew and jitter, then reliability improves, but applicability is limited to certain memory circuit types
Solution Approach 1:
The fast-bypass memory circuit provides a universal solution that can be applied to various memory circuit types. The dual-path architecture with selection logic is a generalizable structure that works with different memory technologies and clocking schemes, making time-borrowing-like functionality accessible beyond traditional memory circuit implementations.
Data Source
AI summary
A memory circuit in which a level of a first data input appears promptly at an output in response to a clock pulse received. The circuit includes a flip-flop triggered by the clock pulse and configured to receive the first data input and drive a second data input. The circuit also includes a first control input driven by the clock pulse, a second control input driven by the flip-flop and selection logic configured to receive the first and second data inputs and the first and second control inputs. The selection logic is configured to drive the output of the memory circuit to the level of the first data input or of the second data input depending on the first and second control inputs.