Fast Chirp PLL Return Boosting for Overshoot Control
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Solution Overview
Problem
Advanced radar systems face challenges in maintaining low phase noise and ramp linearity due to frequency overshoot and PLL unlock during fast chirp modulation, which corrupts radar signal integrity.
Innovation Solution
A boost current is determined and applied to the PLL filter stage during the return phase, proportional to the slope of the return phase and inversely proportional to the VCO gain, to control the frequency transition from stop to start frequency, reducing frequency overshoot and improving PLL settling time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the PLL bandwidth is set to a relatively low value to filter out noise contributions, then phase noise is reduced, but the ramp linearity deteriorates during fast chirp modulation
Solution Approach 1:
The patent applies dynamics by making the PLL bandwidth adjustable rather than fixed. The system dynamically switches between a first bandwidth during the chirp phase (to maintain ramp linearity) and a second, narrower bandwidth during the return phase (to filter noise and reduce frequency overshoot). This temporal variation in bandwidth allows the system to optimize both ramp linearity and phase noise performance at different operational stages.
Solution Approach 2:
The patent changes the bandwidth parameter of the PLL filter based on the operational phase. By adjusting the filter bandwidth from a wider setting during chirp to a narrower setting during return, the system adapts its frequency response characteristics to meet different performance requirements. This parameter change enables the system to achieve both good ramp linearity during frequency sweeping and low phase noise during frequency holding.
2Manufacturing precision
If the PLL bandwidth is increased to improve ramp linearity, then frequency response improves, but phase noise increases
Solution Approach 1:
The system dynamically adjusts the PLL bandwidth based on operational phase requirements. During the chirp phase, a wider bandwidth is used to maintain good ramp linearity and frequency response. During the return phase, the bandwidth is reduced to filter noise and minimize frequency overshoot. This dynamic adjustment resolves the contradiction by applying different bandwidth settings at different times rather than compromising with a fixed intermediate value.
Solution Approach 2:
The patent implements periodic switching between two bandwidth configurations synchronized with the chirp-return cycle. The wider bandwidth is applied periodically during chirp intervals, and the narrower bandwidth is applied periodically during return intervals. This periodic action allows the system to achieve both good ramp linearity and low phase noise performance through time-multiplexed optimization.
3Measurement precision
If fast chirp modulation is used to increase radar resolution, then radar resolution improves, but frequency overshoot and PLL unlock occur during return phase
Solution Approach 1:
The patent applies preliminary anti-action by pre-adjusting the PLL bandwidth before the return phase begins. The system switches to a narrower bandwidth setting during the return phase proactively, before frequency overshoot or PLL unlock can occur. This preemptive adjustment prevents the harmful effects rather than correcting them after they happen, maintaining signal integrity during fast chirp modulation.
Solution Approach 2:
The system uses feedback by monitoring the operational phase (chirp vs. return) and adjusting the PLL bandwidth accordingly. The bandwidth adjustment is triggered by the phase state, creating a feedback mechanism that automatically optimizes the frequency response to prevent overshoot and maintain lock during fast modulation transitions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for a controlled and rapid return to the start frequency, minimizing noise and maintaining linearity, thereby enhancing radar signal integrity and reducing design restrictions on noise and power consumption.
Implementation Method 1
A boost circuit is connected to the digital controller and the filter. The boost circuit supplies a boost current during the return phase
Data Source
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AI summary
A fast chirp Phase Locked Loop (70) with a boosted return time includes a Voltage Controlled Oscillator, VCO, (12) generating a Frequency Modulated Continuous Waveform, FMCW, (14). The VCO responds to a filtered output voltage (74) of a filter (72) connected to a charge pump (28). A digital controller (82) modifies the FMCW to generate a chirp phase (304) and a return phase (300). The chirp phase includes a first linear change of the FMCW from a start frequency (202) to a stop frequency (204). The return phase includes a second linear change of the FMCW from the stop frequency to the start frequency. A boost circuit (86) connects to the digital controller and the filter. The boost circuit supplies a boost current (98) during the return phase. The boost current is proportional to a return slope of the return phase and inversely proportional to a VCO gain of the VCO.