Fast Close Path Fused Multiply-Adder Circuit

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Solution Overview

Problem

Conventional fused multiply-adder circuits have excessive logic depth and high latency due to their critical close path structure, which affects the performance of floating-point operations in digital signal processing and graphics processing.

Innovation Solution

A fast close path circuit is introduced in the fused multiply-adder circuit, utilizing compressors, leading zero anticipators, and adders to process and combine operands in parallel, reducing gate depth and latency by splitting the data-path into multiple paths and eliminating the need for massive aligner components.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If conventional fused multiply-adder circuits are used, then the circuit can perform multiply-accumulate functions, but the logic depth is excessive and latency is high

Engineering Contradiction:

Improveoperation speedVSAvoidlogic depth

Core Design Contradiction:

SpeedVSDevice complexity

Solution Approach 1:

The data-path is divided into multiple parallel paths (first data-path, second data-path, third data-path) that process different portions of the operands simultaneously. This segmentation allows the circuit to avoid the excessive logic depth of conventional serial processing while maintaining the multiply-accumulate function.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The invention transitions from a single sequential processing path to a multi-dimensional parallel architecture where multiple data-paths operate concurrently. This dimensional expansion from 1D serial processing to 2D/3D parallel processing reduces the critical path length and logic depth.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Loss of time

If conventional close path structure is used, then the circuit can normalize and round results, but the latency is high due to serial event chain

Engineering Contradiction:

ImprovelatencyVSAvoidoperation throughput

Core Design Contradiction:

Loss of timeVSProductivity

Solution Approach 1:

Leading zero anticipators are introduced to detect and count leading zeros in the result sum vector before the full addition is complete. This preliminary action allows the normalization process to begin earlier and in parallel with subsequent operations, reducing the overall latency of the close path.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

Multiple operations (addition, leading zero detection, normalization, rounding) are overlapped and executed in parallel across different data-paths rather than sequentially. This continuous parallel execution eliminates idle time and reduces latency while increasing throughput.

Inventive Principle:

Principle #20Continuity of useful action

Data Source

PatentUS10108397B2Fast close path solution for a three-path fused multiply-add design

Publication Date: 2018.10.23 SAMSUNG ELECTRONICS CO LTD

AI summary

Embodiments of the inventive concept include a fast close path solution and circuit of a three path fused multiply-adder circuit. The fast close path circuit can include one or more compressors that can receive multiple operands and produce a result sum and a result carry. The close path circuit can include one or more leading zero anticipators (LZAs). The one or more LZAs can receive and process the result sum and the result carry. The close path circuit can include one or more adders. The one or more adders can receive and add the result sum and the result carry in parallel with the one or more LZAs processing the result sum and the result carry. Since the close path is the critical timing path, by performing the addition operations in parallel with the LZA and/or priority encode (PENC) operations, the logic depth and latency of the close path are reduced.