Fast Data Timing Alignment in Stacked Memory via Dynamic State Machine
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Solution Overview
Problem
In semiconductor memory devices, PVT variations cause delays in data propagation through TSVs between core and interface dies, leading to timing misalignment and potential data overlap, which existing alignment circuits address slowly and inadequately, especially under systemic errors like voltage drift.
Innovation Solution
The implementation of a data aligner circuit with counters and a state machine that enters a fast alignment mode (CFAM) when systemic errors are detected, allowing for rapid adjustments without averaging to correct timing delays across core dies, ensuring predictable data arrival times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional alignment circuits are used to correct timing delays, then data alignment is achieved, but the alignment speed is slow and inadequate under systemic errors
Solution Approach 1:
The alignment circuit dynamically switches between two operational modes: a default mode for normal conditions and a fast alignment mode (CFAM) for systemic errors. The state machine monitors phase detector signals and transitions modes based on detected conditions, enabling the system to adapt its alignment speed and methodology according to real-time requirements.
Solution Approach 2:
The system changes operational parameters by entering CFAM mode when systemic errors are detected. In CFAM mode, the circuit performs rapid coarse adjustments to delay elements without averaging, fundamentally changing the alignment approach from slow precision adjustment to fast correction, thereby improving response time under voltage drift conditions.
2Measurement precision
If averaging is used in alignment circuits to reduce noise, then measurement precision improves, but response time to systemic errors increases
Solution Approach 1:
The system dynamically adjusts its measurement approach based on operational mode. In default mode, averaging is applied to improve measurement precision. When systemic errors are detected and CFAM is entered, averaging is suspended and rapid coarse adjustments are made, dynamically switching between precision and speed based on system conditions.
Solution Approach 2:
The alignment process is segmented into two distinct phases: a default phase with averaging for precision and a CFAM phase without averaging for speed. This segmentation allows the system to apply the appropriate measurement strategy for each condition, avoiding the trade-off by using different methods for different purposes.
3Speed
If fast alignment mode is entered to correct systemic errors rapidly, then alignment speed improves, but complexity of the control system increases
Solution Approach 1:
A state machine acts as an intermediary between the phase detector and the delay elements. It monitors phase detector signals, determines when systemic errors occur, and controls the switching between default mode and CFAM mode. This intermediary manages the complexity by providing a clear control logic that automatically transitions modes based on detected conditions.
Solution Approach 2:
The alignment system is self-managing through automatic mode transitions. The state machine continuously monitors phase detector outputs and autonomously decides when to enter or exit CFAM mode based on detected patterns, eliminating the need for external control logic and reducing overall system complexity while maintaining fast response capability.
Data Source
AI summary
Apparatuses, systems, and methods for data timing alignment with fast alignment mode. A stacked memory device includes an interface die and a number of core die. The interface and the core die each have an adjustable delay circuit adjusted by an interface delay code or a respective core delay code. The delay codes are adjusted based on a measured phase difference along a replica path. In a default maintenance state, the delay codes may be adjusted based on an average of the phase differences over time. Each time the phase difference matches a previous phase difference, the interface die changes a count value associated with that core die. If one or more of the count values cross a threshold, a state machine of the interface die enters a different delay adjustment state where averaging is not used. This may allow for correction of systemic errors such as voltage drift.