Fast Direct Feedback DFE Circuit for High-Speed Data Channels
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Solution Overview
Problem
Conventional decision feedback equalization (DFE) approaches in receiver circuits are too slow and power-consuming for high-speed data channels, making them impractical for Gigabit-per-second and higher data rates due to latency and increased power and area requirements.
Innovation Solution
The implementation of a fast direct feedback decision feedback equalizer (FDF-DFE) system that uses a multiplexer to select between positive and negative reference signals based on a decision feedback signal from the previous clock cycle, allowing for direct comparison with the input data signal to generate an updated decision feedback signal in the same clock cycle, thereby reducing latency and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional decision feedback equalization (DFE) approaches are used, then inter-symbol interference can be corrected, but the circuit exhibits high latency and high power consumption making it impractical for high-speed data channels
Solution Approach 1:
The patent segments the DFE circuit into two independent parallel paths: a data path that processes incoming data signals and an interference path that generates interference signals from previous decisions. This segmentation allows simultaneous processing without sequential delays, reducing latency while maintaining ISI correction capability through the parallel architecture.
Solution Approach 2:
The patent implements preliminary action by pre-computing interference signals in advance using the interference path, which operates independently and continuously generates expected interference based on previous decisions. This pre-computed interference is then subtracted from the data path output, eliminating the need for sequential processing and reducing latency.
2Reliability
If conventional decision feedback equalization (DFE) approaches are used, then inter-symbol interference can be corrected, but the circuit consumes excessive power and occupies excessive area
Solution Approach 1:
The patent extracts the interference cancellation function from the main data processing path by creating a separate interference path. This extraction allows the interference correction to be performed independently using simplified circuitry that only needs to generate and subtract interference signals, rather than processing full data signals, thereby reducing power consumption and area requirements.
Solution Approach 2:
The patent applies local quality by using different circuit configurations in different parts of the DFE: the data path uses high-precision comparators for accurate decision-making, while the interference path uses simpler circuitry optimized for generating interference signals. This localized optimization reduces overall power consumption and area while maintaining ISI correction effectiveness.
3Reliability
If conventional decision feedback equalization (DFE) approaches are used, then inter-symbol interference can be corrected, but the circuit complexity increases making it impractical for very high-speed links
Solution Approach 1:
The patent segments the DFE into modular functional blocks: a data path block, an interference path block, and a combining block. This modular segmentation simplifies the overall circuit design by breaking down the complex DFE into manageable, independent modules that can be designed and optimized separately, reducing overall circuit complexity while maintaining ISI correction capability.
Solution Approach 2:
The patent merges the data path and interference path outputs at a combining stage where the interference signal is subtracted from the data signal. This merging point integrates the functions of both paths in a single operation, simplifying the overall circuit architecture by eliminating the need for separate complex processing stages for each function.
Data Source
AI summary
Embodiments include systems and methods for providing fast direct feedback to correct decision feedback equalization (DFE) in receiver circuits. Embodiments can provide direct feedback for DFE correction in a manner that is effective in high-speed data channels, while manifesting less latency, power consumption, and/or area than conventional DFE implementations. In some implementations, in each clock cycle (e.g., Tn), implementations can select (e.g., using a multiplexer) between a positive reference signal and a negative reference signal (e.g., both reference signals generated according to an inter-symbol interference magnitude for a data channel) according to a decision feedback signal from a previous clock cycle (Tn−1). The selected reference signal can be compared (e.g., in the same clock cycle Tn, using a comparator) with an input data signal to generated an updated decision feedback signal for a next clock cycle (e.g., Tn+1).