Fast Equalization Method for PCIe and CCIX Link Stability
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Solution Overview
Problem
The existing link equalization processes in PCIe and CCIX bus standards are excessively long, leading to potential system errors and timeouts, particularly due to chip aging and temperature changes, necessitating a method to reduce the duration of link equalization.
Innovation Solution
A fast equalization method that stores and reuses previously determined equalization parameters and timeout durations to quickly achieve bit/symbol locking and adjust parameters to meet link stability requirements, ensuring the link equalization process is completed within a shorter timeframe, thereby reducing the risk of system timeouts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the link equalization process is performed using conventional methods, then the link stability requirement is met, but the equalization duration is excessively long causing system timeouts
Solution Approach 1:
The patent stores equalization parameters from previous successful equalization operations in advance. When a link repair is needed, these pre-stored parameters are reused instead of performing a complete equalization process, thereby dramatically reducing the time required while maintaining link stability.
Solution Approach 2:
The patent copies equalization parameters from a previous successful equalization operation (N-a)th time to the current Nth equalization operation. This copying approach allows the system to reuse proven parameters that already meet link stability requirements, avoiding the need to重新 determine parameters and significantly shortening the equalization duration.
2Reliability
If the equalization timeout duration is extended to ensure link stability, then link repair reliability improves, but the system software may still timeout considering the link unavailable
Solution Approach 1:
The system performs equalization parameter determination in advance during the (N-a)th operation and stores these parameters for future use. This preliminary action ensures that when the Nth equalization is needed, the parameters are already available, allowing the equalization timeout to be set to a relatively short duration while still achieving successful link repair.
Solution Approach 2:
By copying proven equalization parameters from previous successful operations, the system ensures link repair reliability without needing to extend the timeout duration. The copied parameters have already been validated to meet link stability requirements, so their reuse guarantees successful repair within a shorter time frame.
3Reliability
If complete equalization parameters are determined each time, then link stability is ensured, but the equalization process consumes excessive time
Solution Approach 1:
The patent copies equalization parameters from a previously successful equalization operation instead of determining complete parameters anew each time. This copying approach maintains link stability because the copied parameters have already been validated to meet stability requirements, while dramatically reducing the equalization process time.
Solution Approach 2:
The system recovers and reuses equalization parameters from previous successful operations rather than discarding them and determining new parameters each time. This recovery approach ensures link stability by using proven parameters while minimizing the time required for the equalization process.
Data Source
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AI summary
This application provides a fast equalization method, to reduce duration required in a link equalization process. The method includes: storing a receive parameter and a transmit parameter, of each of a primary chip and a secondary chip, that meet a link stability requirement and that are obtained when link equalization is previously performed; and when determining that link equalization needs to be performed, configuring, as first fast equalization timeout duration, a larger value in initial fast equalization timeout duration of the primary chip and initial fast equalization timeout duration of the secondary chip, and invoking first equalization parameters, so that the primary chip and the secondary chip perform a current time of link equalization based on the first fast equalization timeout duration and the foregoing transmit and receive parameters, where the first fast equalization timeout duration is equalization timeout duration that is of the primary chip in a third phase of equalization and that exists when the current time of link equalization is performed and equalization timeout duration that is of the primary chip in a fourth phase of equalization and that exists when the current time of link equalization is performed, and is equalization timeout duration that is of the secondary chip in the third phase of equalization and that exists when the current time of link equalization is performed and equalization timeout duration that is of the secondary chip in the fourth phase of equalization and that exists when the current time of link equalization is performed. Further, this application further provides an apparatus and a communications system for performing the method, and a chip mentioned in performing the method.