Fast Filter Processor Pipelined Slices for 10 GE Scalability
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Solution Overview
Problem
Current fast filter processors in packet switched networks struggle to scale with increasing bandwidth, fail to classify and filter packets across multiple ports effectively, and lack flexibility in selecting filter bits, making them inadequate for future high-bandwidth devices with multiple 10 GE ports.
Innovation Solution
The implementation of a fast filter processor with a pipelined architecture that includes multiple slices, each using Ternary Content Addressable Memory (TCAM) for packet classification and range checking, allowing for flexible filtering and increased bandwidth support by processing multiple packets per clock cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If current fast filter processor architecture is used, then device complexity is reduced, but bandwidth scalability deteriorates and cannot support future 10 GE ports
Solution Approach 1:
The fast filter processor is divided into multiple slices, each slice containing its own TCAM and associated logic. This segmentation allows parallel processing of multiple packets simultaneously, enabling the device to scale to higher bandwidths (10 GE ports) while maintaining manageable complexity within each slice. The modular slice architecture can be replicated to match required bandwidth capacity.
Solution Approach 2:
The patent introduces a new dimensional approach by implementing pipelined architecture across multiple slices, allowing packets to be processed in different stages of the pipeline simultaneously. This multi-dimensional processing approach enables the system to achieve high bandwidth scalability without proportionally increasing the complexity of individual processing elements.
2Productivity
If current searching mechanisms are used, then device complexity is minimized, but classification performance deteriorates under increased bandwidth requirements
Solution Approach 1:
The searching mechanism is segmented into multiple slices, each with its own TCAM (Ternary Content Addressable Memory). This segmentation enables parallel search operations across multiple packet streams simultaneously, dramatically increasing classification throughput for high bandwidth applications while keeping each individual search mechanism relatively simple.
Solution Approach 2:
The patent employs multiple copies of the TCAM-based searching mechanism across different slices. Each slice contains a complete copy of the classification logic and TCAM structure, allowing identical search operations to be performed in parallel on different packets or packet segments, thereby scaling throughput without increasing the complexity of the base searching mechanism.
3Adaptability or versatility
If current fast filter processor is used, then device complexity is low, but filtering flexibility deteriorates and cannot filter on bits beyond first 80 bytes
Solution Approach 1:
The fast filter processor implements dynamic field selection capabilities that allow different packet fields to be selected for filtering based on configuration requirements. The pipelined slice architecture enables dynamic access to various packet fields beyond the first 80 bytes, with each slice capable of being configured to filter on different fields as needed, providing high filtering flexibility without requiring a completely rigid processor design.
4Adaptability or versatility
If current fast filter processor is used, then device complexity is reduced, but multi-port packet classification capability deteriorates
Solution Approach 1:
The processor architecture is segmented into multiple slices that can independently handle classification for different ports. Each slice can be configured to handle specific port combinations, enabling the system to perform multi-port packet classification simultaneously. This segmentation approach allows the device to support multiple 10 GE ports with full classification capability on each port without creating a monolithic complex processor.
Data Source
AI summary
A network device for processing packets. The network device includes applying specific fields from a packet to an associated memory device and comparing means for comparing input to the memory device with entries in the memory device. The network device also includes enabling means for enabling selection of bits, by the memory device, that are required to match exactly with bits from the input to the memory device. The network device further includes outputting means for outputting an address for a matched entry by the memory device and applying means for applying a match from the memory device to an associated entry in a table for applying actions from the table that are associated with the match to the packet.