Fast-Locking Delay-Locked Loop for Single-Cycle Clock Recovery
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Delay locked loops (DLLs) face challenges in achieving short lock-times, particularly in clock data recovery applications where rapid phase alignment with bit boundaries is necessary, especially when synchronization patterns are short or data streams lack accompanying clock signals.
Innovation Solution
The implementation of a fast-locking DLL with a delay chain, sampling circuit, transition detector, tri-state buffers, phase discriminator, and control code generator, which determines and adjusts delays to achieve phase-lock within a single clock cycle by selecting the appropriate delayed bit stream and using error signals to maintain phase alignment between the clock and data bit streams.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If conventional delay locked loop design is used, then the circuit structure is simple, but the lock-time is long
Solution Approach 1:
The patent implements preliminary action by using a transition detector to identify bit transitions in advance and a code generator to pre-calculate the appropriate delay tap selection. This allows the DLL to jump directly to the correct phase alignment point rather than gradually adjusting through multiple clock cycles, achieving single-cycle lock-time while managing circuit complexity through functional decomposition into detector, calculator, and selector components.
2Loss of time
If fast-locking mechanism is implemented, then the lock-time is short, but the circuit complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the fast-locking mechanism into distinct functional modules: a transition detector that monitors bit transitions, a code generator that calculates delay tap selections, and a multiplexer that selects the appropriate delayed signal. This modular segmentation achieves fast locking while managing circuit complexity by assigning specific functions to separate components rather than using a monolithic complex circuit.
Solution Approach 2:
The patent uses an intermediary approach by introducing a code generator as a mediator between the transition detector and the delay element selection. The code generator translates transition detection information into specific delay tap selection codes, acting as an intelligent intermediary that enables fast locking without requiring direct complex interconnections between all components, thus managing overall circuit complexity.
Data Source
AI summary
A fast locking delay-locked loop (DLL), which can also operate as a clock data recovery circuit (CDR), includes a delay chain, a sampling circuit and a transition detector. An input signal and delayed versions of the input signal generated by the delay chain are sampled by the sampling circuit. The outputs of the sampling circuit are provided to a transition detector which selects one of the input signal and its delayed versions determined to have signal transitions most closely aligned with a sampling edge of a clock. The selected signal and the clock are provided as inputs to a phase discriminator which generates an error signal representing a level of phase mismatch between the inputs. The error signal is fed back to the sampling circuit to maintain phase lock between the clock signal and the input bit stream.