Fast-Locking Phase-Locked Loop with Reset Signal Control
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Solution Overview
Problem
Existing phase-locked loops face challenges in achieving fast locking due to mutual constraints between stability, dynamic response, accuracy, and noise, leading to long phase-locking times, especially when dealing with significant initial phase errors between reference and feedback signals.
Innovation Solution
A fast-locking phase-locked loop is introduced, incorporating a fast-locking control unit with a rising edge triggered D-type flip-flop that generates a reset signal to reduce initial phase errors, connected to a phase frequency detector and frequency divider, allowing for quicker alignment of feedback and reference signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If conventional phase-locked loop design is used, then stability and accuracy are maintained, but phase-locking time is long
Solution Approach 1:
The patent applies preliminary action by pre-setting the initial phase of the feedback signal to match the reference clock phase before the phase-locked loop begins normal operation. This is achieved through a fast-locking control unit that generates a reset signal at a high level in response to the rising edge of the reference clock signal, which triggers the frequency divider to align the feedback signal phase with the reference signal phase in advance, thereby eliminating initial phase errors and significantly reducing phase-locking time without compromising stability
2Speed
If fast-locking control unit with reset signal is added, then phase-locking speed is improved, but device complexity increases
Solution Approach 1:
The patent applies universality by designing the fast-locking control unit with a rising edge triggered D-type flip-flop that serves multiple functions: it detects the rising edge of the reference clock signal, generates the reset signal at the appropriate timing, and controls the frequency divider to align the feedback signal phase. This multi-functional design achieves fast phase-locking without requiring separate dedicated circuits for each function, thereby minimizing the increase in device complexity while maximizing phase-locking speed
Data Source
AI summary
A fast-locking phase-locked loop comprises a phase frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator, a frequency divider, and a fast-locking control unit which receives a reference clock signal at its first input terminal and a phase-locking enable signal at its second input terminal and outputs a reset signal at a high level in response to a rising edge of the reference clock signal when receiving the phase-locking enable signal, wherein the frequency divider is connected to an output terminal of the fast-locking control unit and configured to trigger generation of a feedback signal in response to the reset signal at the high level, and the phase frequency detector is connected to the output terminal of the fast-locking control unit and configured to output a phase error between the reference clock signal and the feedback signal in response to the reset signal at the high level.