Fast Non-Volatile Memory Direct Host Adapter Access

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Solution Overview

Problem

Data storage arrays face performance limitations due to latencies associated with transferring data to global memory before it is provided to host adapters, even when using faster non-volatile memory devices like flash storage.

Innovation Solution

Implementing a system that transfers data from a cache memory to either the host or host adapter if it is in cache, from slow non-volatile memory to cache and then to the host or adapter if it is in disk memory, and simultaneously to both if it is in fast non-volatile memory, with the option to transfer directly from fast non-volatile memory to the host, using flash memory and disk memory configurations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If data is transferred through global memory to host adapters, then data storage array can use standard memory architecture, but latency increases and performance decreases

Engineering Contradiction:
Improvedata transfer reliabilityVSAvoiddata transfer latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent extracts the fast non-volatile memory from the standard memory hierarchy and creates a direct data path from this memory to the host adapter, bypassing the global memory for certain data transfers. This extraction allows hot data to be served directly without going through the slower global memory path, thereby reducing latency while maintaining system reliability.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The host adapter serves as an intermediary between the fast non-volatile memory and the host system. It manages data transfers directly from the fast memory without requiring global memory involvement, acting as a mediator that enables optimized data paths while maintaining system coherence and reliability.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Speed

If flash storage replaces disk drives, then storage speed improves, but latency from global memory transfer remains

Engineering Contradiction:
Improvestorage access speedVSAvoidglobal memory transfer latency
Core Design Contradiction:
SpeedVSLoss of time

Solution Approach 1:

The system performs preliminary actions by pre-loading frequently accessed data into the fast non-volatile memory before it is actually needed by the host. This anticipatory loading ensures that when data is requested, it is already positioned in the fast memory ready for direct transfer to the host adapter, eliminating the global memory transfer latency step.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces a new dimension to the data path by creating a parallel transfer path that bypasses the traditional sequential flow through global memory. This dimensional change in the data architecture allows simultaneous operations where hot data can be served directly from fast non-volatile memory while other data continues to use the global memory path.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Productivity

If data is cached in global memory, then data access is faster than disk, but still slower than direct fast memory access

Engineering Contradiction:
Improvedata access throughputVSAvoidcache to host transfer time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent segments the memory hierarchy into distinct functional zones: hot data resides in fast non-volatile memory with direct host adapter access, warm data uses global memory cache, and cold data remains on disk. This segmentation allows each segment to be optimized independently, with the hot data segment achieving maximum throughput through direct access paths that eliminate unnecessary transfer steps.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS10318171B1Accessing fast memory in a data storage array
Publication Date: 2019.06.11 EMC IP HLDG CO LLC
  • US10318171B1 patent drawing
  • US10318171B1 patent drawing
  • US10318171B1 patent drawing

AI summary

Providing access to a host for requested data in a data storage array includes transferring the requested data from a cache memory of the data storage array to either the host or a host adaptor if the requested data is in the cache memory, transferring the requested data from a relatively slow non-volatile memory of the data storage array to the cache memory and subsequently transferring the requested data from the cache memory to either the host or the host adaptor if the requested data is in the relatively slow non-volatile memory and transferring the requested data simultaneously to the cache and to either the host and the host adaptor if the requested data is stored in relatively fast non-volatile memory. Data may be transferred directly from the relatively fast non-volatile memory to the host. The relatively fast non-volatile memory may be controlled by the host adaptor.