Fast Path Interrupt Injection for Low Latency
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Solution Overview
Problem
Current computing systems that directly inject hardware interrupts into the operating system are susceptible to surreptitious attacks and incur significant latency due to extensive security and management processing, which is not always necessary for all interrupts.
Innovation Solution
Implementing a system that maintains an eligibility indicator for each interrupt to determine if it can be processed via a fast path, bypassing unnecessary operations and directly injecting it into the operating system, thereby reducing latency and maintaining security.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If hardware interrupts are directly injected into the operating system, then processing latency is reduced, but the system becomes susceptible to surreptitious attacks
Solution Approach 1:
The interrupt processing path is segmented into two distinct paths: a fast path for trusted interrupts and a slow path for untrusted interrupts. The eligibility indicator segments the interrupt stream, allowing most interrupts to take the fast path while routing suspicious ones through the slow path for security processing. This segmentation resolves the contradiction by providing both low-latency processing for normal interrupts and security verification when needed.
Solution Approach 2:
The system performs preliminary security processing during interrupt setup and eligibility determination, before the actual interrupt handling. By pre-evaluating interrupt eligibility and setting up the appropriate processing path in advance, the system ensures security checks are completed beforehand, allowing fast path interrupts to proceed without delay while maintaining security for untrusted sources.
2Reliability
If extensive security and management processing is performed on all interrupts, then system security is enhanced, but processing latency increases significantly
Solution Approach 1:
Different security processing qualities are applied to different interrupts based on their eligibility status. Trusted interrupts receive minimal processing (fast path) while untrusted interrupts receive comprehensive security processing (slow path). This local differentiation of processing quality resolves the contradiction by applying security measures only where necessary, reducing overall latency while maintaining security.
Solution Approach 2:
The system applies partial security processing to most interrupts (fast path with eligibility check) and excessive/full security processing only to suspicious interrupts (slow path). This partial action approach resolves the contradiction by performing security verification on the minimum necessary subset of interrupts while maintaining fast processing for the majority of trusted interrupts.
3Reliability
If a hypervisor intermediate layer is introduced for security processing, then the operating system is protected from attacks, but interrupt processing latency increases from hundreds of thousands of cycles to tens of cycles for fast path
Solution Approach 1:
The eligibility indicator acts as an intermediary mechanism between the hardware interrupt source and the hypervisor security processing. It enables the assembly language processing system to make rapid routing decisions without requiring the hypervisor to process every interrupt, thus maintaining security oversight while dramatically reducing latency for trusted interrupts.
Solution Approach 2:
The assembly language processing system performs self-service by autonomously routing interrupts based on the eligibility indicator, without requiring hypervisor intervention for fast path interrupts. This self-service capability resolves the contradiction by allowing the system to handle most interrupts independently at high speed while the hypervisor retains security authority for untrusted interrupts.
Data Source
AI summary
The state of an interrupt is identified. An eligibility value corresponding to the interrupt is generated based on the state of the interrupt. The eligibility value is indicative of whether the interrupt should be processed by a first processing path or a second processing path, the second processing path being lower latency than the first processing path, and the second processing path bypassing operations performed in the first processing path. When an interrupt is received at an assembly language processing system, from a hardware device, the assembly language processing system accesses the eligibility value corresponding to the interrupt and routes the interrupt to the first or second processing path based on the eligibility value.