Nonvolatile Memory Fast Read Page Architecture
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Solution Overview
Problem
Nonvolatile memory devices face challenges in efficiently storing multiple data bits per memory cell while maintaining reliability, leading to storage space loss when using single level cell (SLC) programming across an entire memory block.
Innovation Solution
The implementation of a nonvolatile memory device that includes a fast read page capable of being determined by one read voltage, alongside normal read pages requiring multiple read voltages, allowing for efficient data storage and retrieval while maintaining reliability, similar to SLC programming.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If SLC programming is performed on an entire memory block to maintain data reliability, then reliability is improved, but storage space is lost
Solution Approach 1:
The patent applies local quality by creating a fast read page with specific bit ordering within a memory block, rather than applying SLC programming uniformly across the entire block. This allows the first page to have enhanced reliability characteristics while other pages maintain multi-level cell programming for maximum storage capacity.
Solution Approach 2:
The memory block is segmented into a fast read page and normal read pages. The fast read page uses a special bit ordering scheme that enables reliable data determination with a single read voltage, while other pages use conventional multi-level cell programming, thus resolving the contradiction between reliability and storage space.
2Quantity of substance
If multiple data bits are stored per memory cell to increase storage capacity, then storage capacity is improved, but read speed deteriorates due to requiring multiple read voltages
Solution Approach 1:
The patent creates a local region (fast read page) with special bit ordering properties that enable fast reading, while other regions maintain high-density multi-level cell programming. This allows the system to achieve both high storage capacity and fast read speed for frequently accessed data.
Solution Approach 2:
The system dynamically adjusts read operations based on page type. For the fast read page, a single read voltage is sufficient, providing fast access. For other pages, multiple read voltages are used to maintain high storage capacity, thus resolving the speed-capacity tradeoff.
3Speed
If SLC programming is used to achieve fast read speed, then read speed is improved, but storage capacity is reduced
Solution Approach 1:
The memory block is divided into a fast read page that uses SLC-like bit ordering for high-speed access and other pages that use multi-level cell programming for high capacity. This segmentation allows the system to achieve both fast read speed and high storage capacity simultaneously.
Solution Approach 2:
A specific page within the memory block is given special local quality through bit ordering that enables fast reading with a single voltage level, while the rest of the memory block maintains high-density programming, thus resolving the speed-capacity contradiction.
Data Source
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AI summary
A nonvolatile memory device including: a memory cell array, the memory cell array including a plurality of cell strings, at least one of the cell strings including a plurality of memory cells stacked in a direction perpendicular to a surface of a substrate, at least one of the memory cells is a multi-level cell storing at least three bits; and a control logic circuit configured to control a page buffer to read a fast read page of the memory cells with one read voltage and at least two normal read pages of the memory cells with the same number of read voltages.