Fast Startup Charge Pump Pre-Charging Circuit
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Solution Overview
Problem
Existing charge pump technologies require either increasing clock frequency or pump capacitor size to achieve faster startup, which introduces noise or increases chip area, respectively.
Innovation Solution
A fast startup charge pump circuit that employs a pre-charging stage to quickly charge the pump and load capacitors, allowing the charge pump to reach steady-state voltage in a shorter time using a lower clock frequency and smaller capacitor size, by disconnecting the pre-charging path and configuring switches for normal operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If clock frequency is increased to achieve faster startup, then startup time is reduced, but noise increases
Solution Approach 1:
The patent applies preliminary action by pre-charging the output capacitor before normal charge pump operation begins. A pre-charge switch connects the output capacitor to the intermediate voltage node during startup, charging it in advance. This eliminates the need to increase clock frequency for faster startup, thereby avoiding noise generation while achieving rapid voltage establishment.
2Loss of time
If pump capacitor size is increased to achieve faster startup, then startup time is reduced, but chip area increases
Solution Approach 1:
The patent uses preliminary action by pre-charging the output capacitor through a dedicated pre-charge switch and path before normal operation. This allows the use of smaller pump capacitors while achieving fast startup, as the output capacitor is charged in advance rather than relying on continuous pumping from small capacitors, thus reducing chip area.
Solution Approach 2:
The patent segments the charging function by separating the pre-charge phase from normal operation phase. A dedicated pre-charge switch and path are provided independently from the normal charge pump switches and capacitors. This segmentation allows optimized capacitor sizing for normal operation while achieving fast startup through the separate pre-charge mechanism, reducing overall chip area.
3Reliability
If number of charge pump stages is increased to achieve lower output voltage, then voltage regulation is improved, but device complexity increases
Solution Approach 1:
The patent applies preliminary action by pre-charging the output capacitor to the target voltage before normal charge pump operation. This eliminates the need for multiple charge pump stages to gradually build up voltage, as the output capacitor is directly charged to the required voltage level in advance. This reduces device complexity while maintaining voltage regulation through the pre-charge mechanism.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The circuit achieves a steady-state voltage in less than one charging pulse time, reducing startup time while maintaining low noise and chip area, with the option to use fewer charge pump stages or even a single stage for quick startup.
Implementation Method 1
the pump capacitor control end is set by the clock control line to a high electrical level, and the clock control end of the pump capacitor of previous stage is at low electrical level, thus there will be displacement current formed by positive charge flowing from pump capacitor of this level to the pump capacitor of previous stage
Data Source
AI summary
A charge pump is designed to be capable of quick start up. When the enable signal of the charge pump is arrived, the pump capacitor and the load capacitor of the charge pump can be charged in a short time, referred to as a pre-charging stage. During the normal working period, the pump capacitor and the output capacitor are controlled by the proper switch that is configured into the connection relationship that the charge pump can normally work in order to make the charge pump work normally. As a result of the pre-charge operation, embodiments disclosed herein can reduce the time of the output capacitor for reaching a steady state value.