Memory Controller ECC Switching by Memory-Area Fatigue
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As memory devices miniaturize and become multivalued, the probability of errors increases, necessitating stronger error correction codes, but existing methods to enhance error correction capability, such as increasing parity data size, lead to increased circuit complexity and reduced user data storage capacity.
Innovation Solution
A memory controller that dynamically adjusts the error correction encoding method based on the fatigue degree of memory areas, switching to higher error correction capabilities when necessary while maintaining a total parity sum below a threshold, thereby improving error correction without increasing circuit scale or data size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the data size of parity is increased to improve error correction capability, then error correction capability is improved, but circuit scale increases and user data storage capacity decreases
Solution Approach 1:
The patent implements dynamic adjustment of error correction capability by switching between different encoding methods (first encoding method with lower error correction capability and second encoding method with higher error correction capability) based on the fatigue degree of memory areas. This allows the system to adapt error correction strength to actual memory conditions rather than using a fixed high-capability encoding scheme, thereby reducing unnecessary circuit complexity while maintaining reliability when needed.
Solution Approach 2:
The patent applies different encoding methods to different memory areas based on their individual fatigue degrees. Memory areas with lower fatigue degrees use the first encoding method (lower error correction capability), while areas with higher fatigue degrees use the second encoding method (higher error correction capability). This localized approach ensures that error correction resources are allocated efficiently only where needed, avoiding the need to increase circuit scale across the entire memory system.
2Reliability
If the data size of parity is increased to improve error correction capability, then error correction capability is improved, but the capacity of user data to be stored decreases
Solution Approach 1:
The system dynamically switches between encoding methods based on memory fatigue degree, allowing the parity data size to be minimized when memory is in good condition (first encoding method) and increased only when necessary (second encoding method). This dynamic approach maximizes user data storage capacity while maintaining error correction capability when needed.
Solution Approach 2:
Different encoding methods with different parity data sizes are applied to different memory areas based on their fatigue degrees. Memory areas in good condition use the first encoding method with smaller parity overhead, preserving more user data capacity. Only areas with high fatigue degrees use the second encoding method with larger parity overhead, thereby minimizing the overall impact on user data storage capacity while maintaining error correction capability where needed.
3Reliability
If a stronger error correcting code is used to handle increased error probability in miniaturized memory, then error correction capability is improved, but circuit complexity and resource allocation increase
Solution Approach 1:
The patent implements a dynamic encoding method selection mechanism that switches between a first encoding method (weaker error correction) and a second encoding method (stronger error correction) based on the fatigue degree of memory areas. This allows the system to use stronger error correcting codes only when and where memory degradation is detected, rather than deploying strong error correction across the entire system, thereby reducing overall circuit complexity and resource allocation while maintaining reliability.
4Reliability
If error correction capability is uniformly increased across all memory areas, then error correction capability is improved, but the parity-to-data ratio becomes imbalanced and resources are wasted
Solution Approach 1:
The patent applies different encoding methods to different memory areas based on their individual fatigue degrees, creating a localized error correction strategy. Memory areas with low fatigue degrees use the first encoding method with lower error correction capability and smaller parity overhead, while areas with high fatigue degrees use the second encoding method with higher error correction capability. This prevents the imbalance of uniformly increasing error correction across all areas, optimizing the parity-to-data ratio and improving overall storage efficiency while maintaining error correction capability where needed.
Data Source
AI summary
According to one embodiment, a nonvolatile memory includes a plurality of memory areas and controller circuit including an error correction code encoder. The error correction code encoder encodes a first data to generate a first parity in a first operation and encodes a second data to generate a second parity in a second operation. The controller circuit writes the first data and the first parity into a first memory area among the plurality of memory areas and writes the second data and the second parity into a second memory area among the plurality of memory areas. The size of the second data is smaller than the size of the first data and the size of the second parity is equal to the size of the first parity.