Fault Address Mapping for Multi-Row Memory Repair
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Solution Overview
Problem
Current memory systems face challenges in efficiently managing content addressable memory (CAM) entries due to the increasing number of defective addresses, leading to resource constraints and inefficient storage of multi-row faults in memory devices.
Innovation Solution
A fault management device and method that stores multiple defective addresses in one CAM entry by masking bits of fault and repair addresses based on multi-row fault information, using a first storage circuit for fault addresses and a second storage circuit for repair addresses, with a mapping control circuit to manage bit masking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If one defective address is stored in one CAM entry using 1:1 entry method, then the storage is simple and direct, but the CAM storage area increases as the number of defective addresses increases, causing resource constraints
Solution Approach 1:
The patent merges multiple defective addresses that share common fault patterns into a single CAM entry. By identifying that multiple sub-word lines may have faults at the same bit positions, the system combines these addresses and stores them together with consolidated repair addresses, reducing the total number of CAM entries required.
Solution Approach 2:
The patent makes a single CAM entry serve multiple functions by storing combined defective addresses that represent multiple fault scenarios. The unified repair address stored in the CAM entry can repair faults across multiple sub-word lines, making the CAM entry universal rather than dedicated to a single address.
2Reliability
If multiple defective addresses are stored in separate CAM entries, then each address can be managed individually, but the limited CAM resources are consumed rapidly, reducing system efficiency
Solution Approach 1:
The patent combines multiple defective addresses into single CAM entries while preserving the ability to accurately manage each address's repair. The merging process identifies commonalities in fault patterns across multiple addresses, allowing consolidated storage that maintains individual address repair capabilities through unified repair address management.
3Quantity of substance
If a large number of CAM entries are allocated to store defective addresses, then all defective addresses can be tracked individually, but the device complexity and resource consumption increase
Solution Approach 1:
The patent reduces device complexity by merging multiple defective addresses into single CAM entries. This consolidation simplifies the CAM entry management structure, reducing the number of entries that need to be individually tracked and managed, while still maintaining comprehensive coverage of all defective addresses through the combined storage approach.
Data Source
AI summary
A fault management device includes a first storage circuit configured to receive and sequentially store a fault address of a memory device and to output a selection signal by comparing stored fault addresses with an input address; a second storage circuit configured to store repair addresses corresponding to the stored fault addresses to output a selected repair address corresponding to the selection signal; and a mapping control circuit configured to control the first storage circuit to mask one or more bits of the received fault address according to a mode information signal indicating faults in two or more sub-word lines, among a plurality of sub-word lines arranged in the memory device, and to control the second storage circuit to mask one or more bits of a repair address corresponding to the masked bits of the received fault address.