Configurable Fault Aggregator for SoC Channel Reduction

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Solution Overview

Problem

In system-on-a-chip (SoC) architectures, the increasing number of processing systems integrated into a single chip leads to a higher likelihood of faults, resulting in a complex fault handling interface and increased gate count and die size due to the need for multiple fault channels.

Innovation Solution

A configurable fault aggregator system that couples each fault source to a demultiplexer, which routes the fault indication to a respective OR gate and then to a single fault channel, allowing for customizable reactions based on the application using the fault source as a resource.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multiple fault channels are used to handle faults from different processing systems, then fault handling reliability is improved, but device complexity and gate count increase

Engineering Contradiction:
Improvefault handling reliabilityVSAvoidfault handling interface complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

Multiple fault channels are merged into a single fault channel through a fault aggregator. The aggregator receives fault indications from multiple processing systems and combines them, allowing a single fault channel to handle faults from multiple sources. This reduces the number of fault channels needed while maintaining the ability to handle faults from different processing systems reliably.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The single fault channel is designed to be universal, capable of handling faults from multiple different processing systems through the fault aggregator. The fault aggregator acts as a multi-functional interface that can route and aggregate fault indications from various sources into a unified fault handling path, making the fault channel adaptable to multiple fault sources.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If multiple fault channels are used to handle faults from different processing systems, then fault handling capability is improved, but the number of gates and die size increase

Engineering Contradiction:
Improvefault handling capabilityVSAvoidgate count and die size
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

Multiple fault channels are merged into a single fault channel through a fault aggregator. The aggregator receives fault indications from multiple processing systems and combines them, allowing a single fault channel to handle faults from multiple sources. This reduces the number of fault channels needed while maintaining the ability to handle faults from different processing systems reliably.

Inventive Principle:
Principle #5Merging (Combining)

3Device complexity

If fault sources are aggregated to a single fault channel using an OR gate, then device complexity is reduced, but the ability to provide different reactions to different fault sources is lost

Engineering Contradiction:
Improvefault handling interface complexityVSAvoidfault reaction adaptability
Core Design Contradiction:
Device complexityVSAdaptability or versatility

Solution Approach 1:

The fault aggregator acts as an intermediary between multiple fault sources and the fault channel. Instead of directly aggregating fault sources with a simple OR gate, the aggregator mediates the fault indications, allowing for more sophisticated handling. The aggregator can route fault indications appropriately while maintaining the ability to provide different reactions based on the specific fault source or type, thus preserving adaptability while reducing complexity.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS12242335B2Method and apparatus for fault aggregation and support for virtualization
Publication Date: 2025.03.04 NXP BV
  • US12242335B2 patent drawing
  • US12242335B2 patent drawing
  • US12242335B2 patent drawing

AI summary

A fault indication from a fault source is to be provided to a demultiplexer which is configured to output the fault indication. The demultiplexer is configurable to output the fault indication to an OR gate of a plurality of OR gates coupled to a respective fault channel of a plurality of fault channels based on an application which uses the fault source as a resource. A reaction to the fault indication is performed based on the fault channel which received the fault indication.