Electric Network Fault Analysis Using Factorized Admittance Matrices
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Solution Overview
Problem
Conventional fault analysis methods for electric networks are computationally intensive and inefficient, particularly for repeated analysis at multiple locations with various fault types, due to the need for frequent matrix inversion and factorization, and they struggle with unbalanced network modeling.
Innovation Solution
The method employs sparse admittance modeling with a single factorization of the pre-fault admittance matrix, allowing for efficient fault analysis at multiple locations using equivalent circuits and factorized matrices, applicable to both balanced and unbalanced systems, reducing computational effort by reusing the pre-fault admittance matrix for various fault types and locations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional impedance based methods are used for fault analysis, then fault analysis can be performed, but the method is both memory-intensive and time-consuming
Solution Approach 1:
The patent performs preliminary factorization of the pre-fault admittance matrix before fault analysis. This factorization is reused for multiple fault locations and types, eliminating the need to repeatedly invert the admittance matrix during fault analysis, thus significantly reducing computation time while maintaining accuracy
Solution Approach 2:
The patent transforms the problem from using impedance matrices to using admittance matrices. By changing the fundamental parameter representation and utilizing the relationship between impedance and admittance, the method achieves computational efficiency through pre-factorization while maintaining the ability to analyze various fault conditions
2Quantity of substance
If admittance matrix-based methods are used for fault analysis, then memory efficiency is improved, but the method is time-consuming due to repeated matrix inversion
Solution Approach 1:
The patent performs the computationally intensive factorization of the admittance matrix in advance, before fault analysis begins. This pre-computed factorization is then reused for analyzing faults at multiple locations and types, eliminating repeated matrix inversions and significantly reducing computation time while maintaining memory efficiency
3Productivity
If compensation-based methods are used for repeated fault analysis, then computation burden is reduced, but the method still involves building and factorizing the admittance matrix for each fault location
Solution Approach 1:
The patent creates a universal pre-fault admittance matrix factorization that serves all fault analysis needs regardless of fault location or type. This single factorization is reused across multiple fault scenarios, eliminating the need to rebuild or refactorize matrices for each specific fault condition, thus simplifying the overall computational procedure while improving efficiency
4Measurement precision
If phase-based methods are used for unbalanced network analysis, then analysis accuracy is improved, but the system becomes very large due to explicit representation of individual phases
Solution Approach 1:
The patent transforms the problem formulation from phase-based to bus-based representation. By changing the fundamental variables and equations to work with bus voltages and currents directly, the method maintains the ability to handle unbalanced conditions while dramatically reducing the system size and complexity compared to explicit phase representation
Data Source
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Figure 4A~4B
AI summary
Fault analysis for an electric network having a plurality of multi-phase buses is performed by computing equivalent circuits for the multi-phase buses of interest. Each equivalent circuit includes an NxN impedance matrix, N corresponding to the number of phases of the multi-phase bus for which that equivalent circuit is computed. Elements of the impedance matrices are determined based on voltages resulting from a plurality of experimental current injection vectors and a factorized pre-fault admittance matrix. The pre-fault admittance matrix represents nodal admittance of the multi-phase buses without faults. A fault current injection vector for each multi-phase bus and fault type of interest is determined based on the equivalent circuit determined for that multi-phase bus. A fault voltage vector for each multi-phase bus and fault type of interest is determined based on the factorized pre-fault admittance matrix and the fault current injection vector determined for that multi-phase bus and fault type.