Fault Analysis Logic Encryption for Low-Overhead IC Protection
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Solution Overview
Problem
The semiconductor industry faces significant losses due to reverse engineering, IP piracy, and malicious circuit insertion during the distributed IC design flow, where existing logic encryption methods are ineffective in concealing functionality and preventing attacks, especially due to performance overhead and collusion risks.
Innovation Solution
The implementation of fault analysis-based logic encryption using XOR/XNOR gates, combined with Physical Unclonable Functions (PUFs) and a simple Logic Encryption Cell (LEC), to ensure that a wrong key affects 50% of output bits and generates unique user keys, preventing collusion and reducing performance overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If logic encryption is implemented using traditional methods, then functionality concealment is achieved, but performance overhead increases significantly
Solution Approach 1:
The patent changes the encryption approach from complex sequential logic to simple combinational XOR/XNOR gates, fundamentally altering the design parameters to achieve encryption with minimal performance impact. This parameter change enables the circuit to maintain high speed while providing security through mathematical properties of XOR operations rather than through complex state machines.
Solution Approach 2:
The patent extracts the encryption functionality from the main data path by using dedicated XOR/XNOR gates that can be selectively activated. The encryption logic is separated into distinct key-controlled gates rather than being embedded throughout the circuit, allowing the core functional logic to operate independently with minimal overhead when encryption is not active.
2Reliability
If logic encryption is implemented to prevent reverse engineering, then security is improved, but area overhead increases
Solution Approach 1:
The patent fundamentally changes the encryption implementation from sequential state machines requiring multiple flip-flops to combinational logic using only XOR/XNOR gates. This parameter change reduces the area overhead dramatically while maintaining security through the mathematical properties of the XOR operation and the secrecy of the key values.
Solution Approach 2:
The patent uses simple, inexpensive XOR/XNOR gates as the encryption mechanism rather than complex security modules. These basic gates provide adequate security when combined with proper key management, avoiding the need for large area-consuming security IP cores or complex cryptographic hardware.
3Reliability
If logic encryption is implemented to prevent IP piracy, then security is improved, but design complexity increases
Solution Approach 1:
The patent simplifies the design by changing from sequential logic encryption to combinational logic encryption. The design complexity is reduced by eliminating state machines, clocks, and synchronization logic, leaving only simple XOR/XNOR gate insertions that are straightforward to integrate into existing combinational logic designs.
Solution Approach 2:
The patent segments the encryption function into individual XOR/XNOR gates that can be independently inserted at specific logic points in the circuit. This segmentation allows the encryption to be applied selectively to critical paths without redesigning the entire circuit, simplifying the integration process.
4Ease of operation
If wrong key affects only one or a few output bits, then ease of operation is improved, but security deteriorates
Solution Approach 1:
The patent applies XOR/XNOR gates at multiple different locations throughout the circuit rather than at a single point. This distributed placement ensures that a wrong key value propagates errors to multiple output bits, with each gate contributing to the overall error pattern. The local quality of each gate's position is optimized to maximize error propagation.
Solution Approach 2:
The patent uses more XOR/XNOR gates than the minimum single gate, applying encryption at multiple strategic points in the circuit. This excessive action ensures that even if one gate's error is masked, other gates will propagate errors to the outputs, making it impossible for a wrong key to produce mostly correct outputs.
Data Source
AI summary
Exemplary systems, methods and computer-accessible mediums can encrypting a circuit by determining at least one location to insert at least one gate in the circuit using a fault analysis, and inserting the at least one gate in at least one section of the at least one location. The determination can include an iterative procedure that can be a greedy iterative procedure. The determination can be based on an effect of the particular location on a maximum number of outputs of the circuit.