Fault-Attack Analysis Device Using Binary Field Addition Encoding

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Solution Overview

Problem

Existing fault-attack analysis methods are ineffective in preventing data encryption and decryption system attacks, as they fail to adequately analyze differential correlations and prevent faults effectively.

Innovation Solution

A fault-attack analysis device and method that includes a controller, encryption and decryption circuit, encoders, decoders, and a comparison circuit, which perform normal and redundant round calculations using binary field addition to detect and analyze faults by comparing decoding results, thereby enhancing security against fault attacks.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional fault-attack analysis methods are used, then the analysis process is simple, but the ability to prevent fault attacks is insufficient

Engineering Contradiction:
Improvefault attack prevention capabilityVSAvoidsystem complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The system divides the encryption process into multiple rounds (normal rounds and redundant rounds) and processes different byte groups separately. Each round handles specific segments of the data, allowing fault attack detection through comparison while maintaining manageable complexity through modular design

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system performs redundant round calculations in advance alongside normal rounds, encoding both results separately. This preliminary action ensures that when a fault attack occurs, the system already has pre-computed results ready for comparison, enabling immediate detection without additional computational overhead during critical operations

Inventive Principle:
Principle #10Preliminary action

2Reliability

If redundant round calculation is performed, then fault detection capability is improved, but calculation time increases

Engineering Contradiction:
Improvefault detection capabilityVSAvoidcalculation time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The system alternates between normal rounds and redundant rounds in a periodic manner, with each type of round serving specific purposes. Normal rounds process data efficiently while redundant rounds provide fault detection coverage, creating a balanced rhythm that optimizes both speed and security

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The system changes operational parameters by switching between different round types (normal vs. redundant) and using different encoding methods (first encoding vs. second encoding based on binary field addition). This parameter variation allows the system to optimize performance for different operational phases while maintaining overall efficiency

Inventive Principle:
Principle #35Parameter changes

3Reliability

If binary field addition encoding is used, then security against fault attacks is enhanced, but encoding complexity increases

Engineering Contradiction:
Improvesecurity against fault attacksVSAvoidencoding complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The system creates encoded copies of the data through binary field addition encoding, generating alternative representations that can be compared for fault detection. These encoded copies serve as security checkpoints without requiring fundamentally new encoding mechanisms, leveraging existing binary field arithmetic operations

Inventive Principle:
Principle #26Copying

Solution Approach 2:

The binary field addition encoding mechanism serves multiple functions simultaneously: it provides data transformation for processing, creates redundancy for fault detection, and enables security verification through comparison. This multi-functionality reduces the need for separate dedicated components for each function

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS20240220606A1Fault-attack analysis device and method
Publication Date: 2024.07.04 NUVOTON
  • US20240220606A1 patent drawing
  • US20240220606A1 patent drawing
  • US20240220606A1 patent drawing

AI summary

An embodiment of the invention provides a fault-attack analysis device. The first encoder performs a first encoding operation on the first output result corresponding to the normal round calculation to generate a first encoding result. The first decoder performs a first decoding operation on the first encoding result to generate a first decoding result. The second encoder performs a second encoding operation on the second output result corresponding to the redundant round calculation to generate a second encoding result. The second decoder performs a second decoding operation on the second encoding result to generate a second decoding result. The second encoding operation and the second decoding operation are based on binary field addition. The comparison circuit compares the first decoding result to the second decoding result to perform a fault-attack analysis.