Fault-Aware Memory Page Offlining for Uncorrectable Error Prediction
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Solution Overview
Problem
Traditional memory failure prediction methods based on correctable error thresholds are unreliable for predicting uncorrectable errors, leading to inefficient and imprecise page offlining in memory systems, which can result in system failures.
Innovation Solution
A fault-aware prediction system that correlates correctable error patterns with memory architecture to identify pages prone to uncorrectable errors, using a model that accounts for circuit-level information such as row, column, or bit-level faults, allowing for more accurate prediction and proactive page offlining.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional threshold-based counting of correctable errors is used for memory failure prediction, then the system can implement simple page offlining based on CE thresholds, but the prediction reliability for uncorrectable errors is insufficient
Solution Approach 1:
The patent segments the memory system into multiple hierarchical levels: memory cells, bit lines, word lines, banks, and pages. By analyzing error patterns at each level separately and correlating them with hardware configuration, the system achieves more reliable UE prediction without excessive complexity. The segmentation allows focused analysis of specific fault types (row faults, column faults, bit faults) rather than treating all errors uniformly.
Solution Approach 2:
The patent transitions from traditional single-dimension CE counting to multi-dimensional analysis by incorporating hardware configuration information (row, column, bit indices) and error pattern characteristics. This dimensional expansion enables the system to distinguish between different types of faults and their progression to UEs, significantly improving prediction reliability while maintaining manageable complexity through structured analysis.
2Measurement precision
If circuit-level information is incorporated into error prediction, then the prediction accuracy for uncorrectable errors improves, but the computational complexity increases
Solution Approach 1:
The patent applies local quality by analyzing error patterns specific to different locations in the memory hierarchy. Instead of uniform error counting, the system examines errors at specific rows, columns, and bits, correlating them with hardware configuration to identify localized faults. This location-specific analysis improves prediction accuracy for UEs while keeping complexity manageable through focused, targeted analysis rather than comprehensive system-wide monitoring.
Solution Approach 2:
The patent performs preliminary analysis of error patterns and hardware configuration correlation to establish prediction models before actual UE occurrence. By pre-processing and categorizing error data according to hardware structure, the system prepares prediction criteria in advance, reducing real-time computational complexity while maintaining high prediction accuracy when evaluating new errors.
3Reliability
If proactive page offlining is implemented based on fault prediction, then uncorrectable error occurrences are reduced, but system resources are consumed for monitoring and prediction
Solution Approach 1:
The patent implements self-service by leveraging existing memory error correction mechanisms and hardware configuration information that are already present in the system. The prediction system reuses existing error logs and hardware metadata without requiring additional sensors or external monitoring equipment, thereby reducing energy consumption while maintaining reliable UE prediction and proactive page offlining capabilities.
Data Source
AI summary
A system can predict what pages of memory the system should offline based on identification of how correctable error patterns correlate to the memory architecture. The failure prediction can account for the circuit-level architecture of the memory rather than the mere number or frequency of correctable errors. A controller correlates the hardware configuration of the memory with historical error data, and generates an estimate of pages for a host operating system (OS) to offline based on predicting uncorrectable errors (UEs).