Fault Detection Circuit Using Capacitive Coupling Against Injection Attacks
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Solution Overview
Problem
Existing integrated circuits are vulnerable to fault injection attacks that manipulate clock frequency or power supply voltage, leading to incorrect computations and security breaches.
Innovation Solution
A fault detection circuit utilizing capacitive coupling between parallel conductors to detect signal transition delays, employing inverters and a checker circuit to identify deviations from expected bit patterns, indicating a fault injection attack.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the device operates at high clock frequency to improve processing speed, then productivity is improved, but the device becomes vulnerable to fault injection attacks that exploit timing vulnerabilities
Solution Approach 1:
The patent implements a preliminary action by executing a test pattern sequence before normal operation to establish expected timing behavior. The fault detection circuit pre-calculates and stores expected signal transition times for various operational modes, enabling subsequent real-time fault detection without requiring complex analysis during actual operation.
Solution Approach 2:
The patent employs feedback mechanisms where the fault detection circuit continuously monitors actual signal transitions and compares them against expected values. When deviations are detected indicating fault injection attempts, the system generates feedback signals that can trigger corrective actions or alert security modules, creating a closed-loop security system.
2Reliability
If the device performs security checks to improve reliability, then security is improved, but computation time increases reducing productivity
Solution Approach 1:
The patent applies preliminary action by performing timing characteristic measurements and fault detection circuit initialization during boot-up or idle periods before actual security-critical operations begin. This pre-characterization approach allows the system to have security verification mechanisms ready without adding significant overhead to real-time authentication processes.
Solution Approach 2:
The patent replaces complex mechanical/security verification procedures with electronic timing analysis. Instead of relying solely on traditional security checks that require multiple computational steps, the system uses electrical signal timing characteristics as proxies for security verification, reducing computational time while maintaining security effectiveness.
3Measurement precision
If the fault detection circuit monitors all signal transitions to improve detection accuracy, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent applies local quality by focusing the fault detection circuit's monitoring capabilities on specific critical signal paths and timing windows rather than attempting to monitor all signals uniformly. The circuit identifies and prioritizes monitoring of signals most vulnerable to fault injection based on their timing characteristics and operational importance, achieving high detection accuracy with reduced circuit complexity.
Solution Approach 2:
The patent uses copying by creating a simplified replica of the timing verification function within the fault detection circuit. Instead of directly analyzing complex signal waveforms in real-time, the circuit generates and compares simplified timing signatures or clock cycles that capture essential timing information, reducing the complexity of the monitoring function while maintaining detection precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Effectively detects fault injection attacks by identifying incorrect bit captures due to manipulated clock frequency or power supply voltage, enabling timely corrective actions to prevent security breaches.
Implementation Method 1
The capacitive coupling between the conductors may cause delay to be introduced in the conducted bit pattern causing the bits to transition from one logic state to another logic state at different times.
Data Source
AI summary
A fault detection circuit includes a plurality of conductors, a plurality of logic gates coupled to the conductors, a storage circuit, and a checker circuit. The conductors are arranged in parallel. Each logic gate is coupled to a first end of each conductor. The storage circuit is coupled to a second end of each conductor. The checker circuit is coupled to the storage circuit. A known initial bit pattern is provided to an input of the logic gates, and an output of the logic gates is provided to the storage circuit via the conductors. The checker circuit determines if the output of the logic gates stored in the storage circuit is an expected result. If the output is not the expected result, then the checker circuit provides an indication that a fault injection attack is occurring. In another embodiment, a method for detecting a fault injection attack is provided.