Fault Detection Circuit Testing via Idle Bus Cycle Multiplexing
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Solution Overview
Problem
Electrical systems face challenges in testing fault detection circuits without disrupting system operation, as disabling these circuits during testing renders the system susceptible to data errors, while pausing the entire system for testing has undesirable effects, especially in real-time critical operations.
Innovation Solution
The system detects idle bus cycles to initiate tests of communication link fault detection circuits using multiplexers, a monitor circuit, and exclusive-OR logic, allowing for fault detection circuit testing during runtime without interrupting data transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If fault detection circuits are disabled during testing, then testing can be performed, but the system becomes susceptible to data errors
Solution Approach 1:
The system performs fault detection circuit testing during idle bus cycles before normal operation resumes. The monitor circuit is configured to capture test data and compare it with expected values, completing the testing action in advance during periods when the bus is not being used for data transmission, thus preventing potential errors from affecting operational data
2Reliability
If the entire system is paused for testing, then fault detection circuits can be tested, but real-time critical operations are interrupted
Solution Approach 1:
The system dynamically switches between operational mode and test mode by utilizing the state of the bus. During idle cycles when no data transmission is occurring, the multiplexers route test data through the fault detection circuits. During active data transmission, the circuits operate normally. This dynamic adaptation allows testing without pausing critical real-time operations
Solution Approach 2:
The fault detection circuits are tested periodically during idle bus cycles that occur naturally in the system operation. Rather than continuous testing or system pausing, the monitor circuit captures test patterns at these periodic intervals when the bus is available, maintaining both system productivity and reliability
3Productivity
If fault detection circuits are tested during runtime, then system operation continues, but testing must be performed without disrupting data transmission
Solution Approach 1:
The monitor circuit serves multiple functions: it captures data during normal operation, captures test data during idle cycles, and compares data against expected values. The same circuit infrastructure is used for both operational monitoring and fault detection testing, eliminating the need for separate dedicated test hardware and reducing overall system complexity
Solution Approach 2:
The fault detection circuits test themselves by processing test data that is routed through the existing multiplexer infrastructure. The monitor circuit uses the same comparison logic it employs for operational data to validate the fault detection circuits, allowing the system to self-test without external testing equipment or complex additional mechanisms
Data Source
AI summary
A system-on-chip includes first and second devices. An interconnect segment couples between the first and second devices. A bridge is coupled between the first and second devices and coupled to the interconnect segment. At least one of the bridge or interconnect segment include first and second multiplexers, a monitor circuit, and exclusive-OR logic. The first multiplexer has first and second multiplexer inputs and a first multiplexer output. The second multiplexer has third and fourth multiplexer inputs and a second multiplexer output. The monitor circuit has a first and second monitor circuit outputs. The first monitor circuit output is coupled to the second multiplexer input and the second monitor circuit output is coupled to the fourth multiplexer input. The exclusive-OR logic has first and second exclusive-OR logic inputs. The first exclusive-OR logic input couples to the first multiplexer output and the second exclusive-OR logic input couples to the second multiplexer output.