Task-Specific Fault Detection Scheduling Table
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Solution Overview
Problem
Current fault detection methods in computer technologies, such as periodically executing test patterns in a software test library, result in a heavy processor load due to the large number of test patterns required, which affects working efficiency and increases fault detection time.
Innovation Solution
A fault detection method that determines a scheduling table specific to a target task, executing only the necessary test patterns to detect faults in the target logic circuit, thereby reducing processor load and improving efficiency by avoiding the execution of all test patterns in the software test library.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all test patterns in the software test library are executed periodically to detect faults, then fault detection coverage is improved, but processor load increases and working efficiency deteriorates
Solution Approach 1:
The patent segments the complete test pattern set into task-specific subsets by creating scheduling tables that map different task types to their required test patterns. Instead of executing all test patterns universally, the system divides the test library into manageable segments corresponding to specific logic circuit functions, executing only the relevant segment for each task.
Solution Approach 2:
The patent extracts and executes only the necessary test patterns from the complete software test library by generating scheduling tables that identify and isolate the specific test patterns required for each target task. This extraction process removes unnecessary test patterns from the execution queue, reducing processor load while maintaining adequate fault detection coverage.
2Measurement precision
If all test patterns in the software test library are executed to ensure comprehensive fault detection, then measurement precision of fault detection is improved, but time consumption increases
Solution Approach 1:
The patent performs preliminary action by pre-generating scheduling tables that map task types to their required test patterns before actual fault detection occurs. This advance preparation allows the system to quickly identify and execute only the necessary test patterns when a task is running, avoiding the time penalty of selecting test patterns in real-time while maintaining precise fault detection capability.
Solution Approach 2:
The patent applies partial action by executing only the subset of test patterns that are actually needed for the current task rather than the complete test library. The scheduling tables enable the system to perform exactly enough testing to detect faults relevant to the target logic circuit without the excess time consumption of running unnecessary test patterns.
3Reliability
If a large quantity of test patterns are executed periodically, then reliability of fault detection is improved, but device complexity increases
Solution Approach 1:
The patent introduces scheduling tables as an intermediary data structure that mediates between the task execution system and the test pattern library. These tables serve as a lookup mechanism that simplifies the complexity of managing large quantities of test patterns by providing a direct mapping from task types to required test patterns, eliminating the need for complex real-time decision-making logic.
Solution Approach 2:
The patent changes the parameter of test pattern selection from a dynamic, complex decision-making process to a static, table-driven approach. By encoding the relationship between tasks and test patterns in scheduling tables, the system transforms the complexity of managing large test pattern quantities into a simple parameter lookup operation, maintaining reliability while reducing operational complexity.
Data Source
AI summary
A fault detection method includes: obtaining a scheduling table of a target task, where the scheduling table is used to indicate at least one test pattern, the at least one test pattern is used to detect a fault in a target logic circuit, and the target logic circuit is a logic circuit configured to execute the target task; and executing the at least one test pattern based on the scheduling table, to detect the fault in the target logic circuit.